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研究生:林宜彥
研究生(外文):Yi-Yan Lin
論文名稱:低溫多晶矽薄膜電晶體之研製與應用
論文名稱(外文):Investigation and Application of Low Temperature Poly-Si Thin Film Transistors
指導教授:范慶麟
指導教授(外文):Ching-Lin Fan
口試委員:范慶麟
口試日期:2012-04-13
學位類別:博士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:123
中文關鍵詞:複晶矽薄膜電晶體快速熱退火多通道結構鈍化技術畫素補償電路
外文關鍵詞:Poly-Si Thin Film TransistorsRapid Thermal Annealingmulti-channelpassivation techniquecompensation pixel design
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在本論文中,我們研究快速熱退火與多通道結構合併製程與鈍化技術對於多晶矽薄膜電晶體之影響,並提供一新穎的畫素補償電路與驅動方法。首先,我們研究快速熱退火與多通道結構合併製程對於薄膜電晶體電氣特性之改善。其研究結果顯示,快速熱退火與多通道結構合併製程是一個有效率提升薄膜電晶體之電氣特性的方法,因為其可以有效的同時減少缺陷與提升閘極絕緣層薄膜之品質,特別在於較薄的閘極絕緣層與短通道之薄膜電晶體。
此外,我們提出三種鈍化之技術以提升多晶矽薄膜電晶體之電氣特性與可靠度,其中包括利用中空陰極化學氣相沉積系統產生之N2電漿處理通道層、利用CF4電漿於緩衝層之前置處理與FSG遮罩驅入薄膜。首先,我們利用中空陰極化學氣相沉積系統產生之N2電漿於通道層進行處理,其研究結果發現利用此系統可同時得到較佳的鈍化效果與較好的鈍化效率,由於平緩的氧化層與多晶矽之介面因其低電漿破壞特性,與理處時較短之擴散距離。
再者,我們利用CF4電漿於緩衝層進行前置處理以提升多晶矽薄膜電晶體之電氣特性。其研究結果顯示氟原子將積累於通道與緩衝層之介面並堆積至通道層,而由氟原子鈍化減少之缺陷將可提升多晶矽薄膜電晶體之電氣特性。由研究結果亦可發現其臨界電壓可由4.32 V減少至3.03 V,且場效載子移動率將由29.71上升至45.65 cm2/V.s。此外,導通電流衰退與臨界電壓偏移將分別大幅度的改善31%與70%。
另外,我們亦利用FSG遮罩驅入薄膜於通道層以提升元件之電氣特性。FSG遮罩驅入薄膜可圖案化並定義通道之源極與汲極,並於活化源極與汲極時同時完成氟原子驅入之鈍化處理,其氟離子可由FSG遮罩驅入薄膜擴散至通道層本體並鈍化其缺陷,因而使多晶矽薄膜電晶體之電氣特性有大幅度之提升,其研究結果顯示場效載子移動率將由10.9上升至30.4 cm2/V.s,其開關電流比將由8.9 × 104 上升至 10.4 × 105。
最後,我們亦提出一新穎之畫素補償電路與驅動方法,此電路利用一回授電路應用於主動有機發光二極體面板,並藉由SPICE模擬其結果。此電路由4個薄膜電晶體與2個電容外加一訊號線所組成。當驅動薄膜電晶體之臨界電壓偏差±0.33 V時,其OLED之陽極電壓變化之錯誤率將低於0.3%。其模擬結果顯示,此補償電路可藉由同時補償驅動薄膜電晶體之臨界電壓偏差與OLED臨界電壓之衰退以改善顯示畫面之不均勻性。
In this thesis, we investigate the effects of RTA and multi-channel combined scheme, passivation techniques of a polycrystalline silicon thin film transistor, and present one novel compensation pixel design and driving method. First, we study the improvement of the electrical characteristics of LTPS TFTs with a combined scheme of RTA and multi-channel structure. The results show that the RTA and multi-channel combined scheme is an effective scheme for improving the electrical characteristics of LTPS TFTs because of the reduction of trap state densities and improvement of gate oxide quality at the same time, and a particularly apparent improvement for LTPS TFTs with a thinner gate oxide and short channel length.
Moreover, we propose three passivation techniques to improve the performance and reliability of LTPS TFTs, including N2 plasma treatment on channel layer using a HCCVD system, CF4 plasma pretreatment on the buffer oxide layer and an FSG drive-in masking layer. First, the scheme for N2 plasma treatment using HCCVD system can simultaneously result in a better passivation effect and higher passivation efficiency, owing to the smooth oxide/poly-Si interface with low plasma damage and shortened diffusion length. Second, we apply CF4 plasma pretreatment to a buffer oxide layer to improve the performance of LTPS TFTs. The results show that the fluorine atoms pile up at the interface between the bulk channel and buffer oxide layer, and accumulate in the bulk channel. Reduction of trap state density by fluorine passivation can improve the electrical characteristics of LTPS TFTs. It is found that the threshold voltage was reduced from 4.32 to 3.03 V and the field-effect mobility increased from 29.71 to 45.65 cm2/V.s. In addition, the on-current degradation and threshold voltage shift after stressing were significantly improved by about 31% and 70%, respectively. Third, we investigated LTPS TFTs with an FSG drive-in masking layer on the channel layer to improve the device’s performance. The FSG drive-in layer can also be patterned as a masking layer to define the source and drain regions, and the activation of the source/drain regions and fluorine passivation can be accomplished simultaneously. The fluorine atoms can diffuse from the FSG drive-in masking layer into the bulk channel to passivate the trap states, resulting in considerable improvement of the electrical characteristics of the device. This result demonstrated that the field effect mobility increased from 10.9 to 30.4 cm2/V.s, and the ON/OFF current ratio increased from 8.9 × 104 to 10.4 × 105.
In addition, we present one novel compensation pixel design and driving method for AMOLED displays with a voltage feedback method; the simulation results are proposed and verified by a SPICE simulator. The proposed circuit consists of four TFTs and two capacitors with an additional signal line. The error rates of an OLED anode voltage variation are below 0.3% under the threshold voltage deviation of driving TFT (ΔVTH = ±0.33 V). The simulation results show that the pixel design can improve the display image non-uniformity by compensating for the threshold voltage deviation of driving TFT and the degradation of OLED threshold voltage at the same time.
摘要 I
Abstract III
致謝 V
Contents VI
Table Captions X
Figures Captions XI
Chapter 1 Introduction 1
1.1 An Overview of Low Temperature Poly-Si Thin-Film Transistor (LTPS TFT) 1
1.2 Electrical Parameters of Poly-Si Thin-Film Transistor 3
1.2.1 Field-Effect Mobility (?媹E) 3
1.2.2 Threshold Voltage (VTH) 4
1.2.3 Subthreshold Swing (S.S.) 4
1.2.4 ON/OFF Current Ratio 5
1.2.5 Trap State Density (Nt) 6
1.3 Motivation 7
1.4 Thesis Organization 9
Chapter 2 Effects of Rapid Thermal Annealing and Multi-channel on LTPS TFT 11
2.1 Introduction 11
2.2 Experimental 12
2.3 Results and Discussion 13
2.3.1 Effects of RTA Treatment 13
2.3.2 Effects of Multi-channel 16
2.4 Conclusion 18
Chapter 3 LTPS TFT with High-Efficiency and Low-Damage N2 Plasma Pretreatment 29
3.1 Introduction 29
3.2 Experimental 30
3.3 Results and Discussion 31
3.3.1 Radio-Frequency Hollow Cathode Plasma System 31
3.3.2 Interface Morphology and Depth Profile of Nitrogen Atoms 32
3.3.3 Device Characteristics 33
3.3.4 Device Reliability 36
3.4 Conclusion 38
Chapter 4 LTPS TFT with CF4 Plasma Pretreatment on the Buffer Oxide Layer 48
4.1 Introduction 48
4.2 Experimental 49
4.3 Results and Discussion 50
4.3.1 Interface Morphology and Depth Profile of Fluorine Atoms 50
4.3.2 Device Characteristics 51
4.3.3 Device Reliability 53
4.4 Conclusion 54
Chapter 5 LTPS TFT with Fluorinated Silicate Glass Drive-in Making Layer 67
5.1 Introduction 67
5.2 Experimental 69
5.3 Results and Discussion 70
5.3.1 Depth Profile of Fluorine Atoms 70
5.3.2 Device Characteristics 70
5.3.3 Device Reliability 72
5.4 Conclusion 73
Chapter 6 A New Low Temperature Polycrystalline Silicon Thin Film Transistor Pixel Circuit for Active Matrix Organic Light Emitting Diode 82
6.1 Introduction 82
6.2 LTPS TFT Fabrication Processes and Electrical Characteristics 84
6.3 Proposed Pixel Circuit and Driving Method 85
6.4 Simulation Result of Proposed Circuit 87
6.5 Conclusion 89
Chapter 7 Conclusions and Further Works 100
7.1 Summary of the Thesis 100
7.2 Further Works 102
References 104
簡 歷 114
Publication List 115
Chapter 1
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[1.3]Kuriyama, H., Okada, T., Ashida, M., Sakamoto, O., Yuzuriha, K., Tsutsunii, K., Nishimura, T., Ananii, K., Kohno, Y., and Miyoshi, H., “An Asymmetric Memory Cell Using A C-TFT for ULSI SRAM”, Symposium on VLSI Technology, pp. 38-39 (1992)
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[1.5]Yoshizaki, K., Takaashi, H., Kamigaki, Y., Asui, T., Komori, K., and Katto, H., “A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme” , ISSCC Digest of Technical Papers, pp.166 (1985)
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[1.9]Yamauchi, N., Inava, U., and Okamura M., “An Integrated Photodetector-Amplifier Using a-Si p-i-n Photodiodes and Poly-Si Thin-Film Transistors” , Photonics Technology Letters, Vol. 5, No, 3, pp. 319-321 (1993)
[1.10]Clark M. G., “Current Status and Future Prospects of Poly-Si Devices” IEE Proceedings of Circuits, Devices and Systems, Vol. 141, No. 1, pp. 3-8 (1994)
[1.11]Jagar, S., Chan, M., Poon, M.C., Wang, H., Qin, M., Ko, P.K., Wang Y., “Single Grain Thin-Film-Transistor (TFT) with SOI CMOS Performance Formed by Metal-Induced-Lateral-Crystallization” , International Electron Devices Meeting Digest, pp. 293-296 (1999)
[1.12]Nakazawa, K., “Recrystallization of Amorphous Silicon Films Deposited by Low‐Pressure Chemical Vapor Deposition from Si2H6 Gas” , Journal of Applied Physics, Vol. 69, pp. 1703-1706 (1991)
[1.13]H., Kuriyama, S., Kiyama, S., Noguchi, T., Kuahara, S., Ishida, T., Nohda, K., Sano, H. Iwata, S. Tsuda, and S. Nakano “High Mobility Poly-Si TFT by a New Excimer Laser Annealing Method for Large Area Electronics” , International Electron Devices Meeting Digest, pp. 563 (1991)
[1.14]Lim, K. M., and Sung, M. Y., “Low Noise Digital Data Driver Circuit Integrated Poly-Si TFT–LCD” , Microelectronics Journal, Vol. 30 pp. 905–910 (1999)
[1.15]Lim, K. M., Lee, K. E., Y. Juhn S., Yoon, J. M., Baek M. K., Yoo, J.-S., Jung, Y. S., Park, J. K., Lee, S. W., Kang, H. C., Kim, C. D., Chung, I. J., “A 3.5 in. QVGA Poly-Si TFT–LCD With Integrated Driver Including New 6-bit” , Solid-State Electronics, Vol. 49, pp. 1107–1111 (2005)
[1.16]Leea, W. K., Hana, S. M., Choib, J., Hana, M. K., “The Characteristics of Solid Phase Crystallized (SPC) Polycrystalline Silicon Thin Film Transistors Employing Amorphous Silicon Process” , Journal of Non-Crystalline Solids, Vol. 354, pp. 2509-2512 (2008)
[1.17]Tai, M., Hatano, M., Yamaguchi, S., Noda, T., Park, S. K., Shiba, and Ohkura, M., “Performance of Poly-Si TFTs Fabricated by SELAX” , IEEE Transactions on Electron Devices, Vol. 51, No. 6, pp. 934-938 (2004)
[1.18]Lee, S. W., and Joo, S. K., “Low Temperature Poly-Si Thin-Film Transistor Fabrication by Metal-Induced Lateral Crystallization” , IEEE Electron Device Letters, Vol. 17, No. 4, pp. 160-162 (1996)
[1.19]Levinson, J., Shepherd, F. R., Scanlon, P. J., Westwood, W. D., Este, G., and Rider, M., “Conductivity Behavior in Polycrystalline Semiconductor Thin Film Transistors” , Journal of Applied Physics, Vol. 53, No. 2, pp. 1193-1202 (1982)
[1.20]Migliorato, P., Reita, C., Tallatida, G., Quinn, M., and Fortunato, G., “Anomalous Off-Current Mechanisms in n-Channel Poly-Si Thin Film Transistors” , Solid-State-Electronics, Vol. 38, pp. 2075-2079 (1995)
[1.21]Hack, M., Wu, I-W., King, T. H., and Lewis, A. G., “Analysis of Leakage Currents in Poly-silicon Thin Film Transistors” , International Electron Devices Meeting Digest, Vol. 93, pp. 385-387 (1993)
[1.22]King, T. J., and Saraswat K.C., “Low-Temperature (≦550℃) Fabrication of Poly-Si Thin-Film Transistors” , IEEE Electron Device Letters, Vol. 13, No. 6, pp. 309-311 (1992)
[1.23]Seto, John Y. W., “The Electrical Properties of Polycrystalline Silicon Films” , Journal of Applied Physics, Vol. 46, No. 12, pp. 5247-5254 (1975)
[1.24]Proano, R. E., Misage, R. S., and Ast, D. G., “Development and Electrical Properties of Undoped Polycrystalline Silicon Thin-Film Transistors” , IEEE Transactions on Electron Devices, Vol. 36, No. 9, pp. 1915-1922 (1989)

Chapter 2
[2.1]Mimura, A., Konishi, N., Ono, K., Ohwada, J., Hosokawa, Y., Ono, Y. A., Suzuki, T., Miyata, K., and Kawakami, H., “High Performance Low-Temperature Poly-Si n-Channel TFT’s for LCD” , IEEE Transactions on Electron Devices, Vol. 36, No. 2, pp. 351-359 (1989)
[2.2]King, T. J., and Saraswat, K. C., “Low-Temperature (≦550℃) Fabrication of Poly-Si Thin-Film Transistors” , IEEE Electron Device Letters, Vol. 13, No. 6, pp. 309-311 (1992)
[2.3]Fan, C. L., and Chen, M. C., “Performance Improvement of Excimer Laser Annealed Poly-Si TFTs Using Fluorine Ion Implantation” , Electrochemical and Solid-State Letters, Vol. 5, No. 8, pp. G75-G77 (2002)
[2.4]Fan, C. L., Lai, H. L., and Yang, T. H., “Enhanced Crystallization and Improved Reliability for Low-Temperature-Processed Poly-Si TFTs With NH3 Plasma Pretreatment Before Crystallization” , IEEE Electron Device Letters, Vol. 27, No. 7 pp. 576-578 (2006)
[2.5]Yeh, C. F., Lin, S. S., and Fan, C. L., “Thinner Liquid Phase Deposited Oxide for Polvsilicon Thin-Film Transistors” , IEEE Electron Device Letters, Vol. 16, No. 11, pp. 473-475 (1995)
[2.6]Lin, P. S., and Li, T. S., “The Impact of Scaling-Down Oxide Thickness on Poly-Si Thin-Film Transistors’ I-V Characteristics” , IEEE Electron Device Letters, Vol. 15, No. 4, pp. 138-139 (1994)
[2.7]Lee, T. S., and Lin, P. S., “On the Pseudo-Subthreshold Characteristics of Polycrystalline-Silicon Thin-Film Transistors with Large Grain Size” , IEEE Electron Device Letters, Vol. 14, No. 5, pp. 240-242 (1993)
[2.8]Bhat, N., Wang, A. W., and Saraswat, K. C., “Rapid Thermal Anneal of Gate Oxides for Low Thermal Budget TFT’s” , IEEE Transactions on Electron Devices, Vol. 46, No. 1, pp. 63-69 (1999)
[2.9]Kao, C. H., and Lai, C. S., “Performance and Reliability Improvements in Thin Film Transistors with Rapid Thermal N2O Annealing” , Semiconductor Science and Technology, Vol. 23, No. 2, p. 025020 (2008)
[2.10]Kao, C. H., Lai, C. S., and Lee, C. L., “Oxide Grown on Polycrystal Silicon by Rapid Thermal Oxidation in N2O” , Journal of The Electrochemical Society, Vol. 153, No. 2, pp. G128-133 (2006)
[2.11]Fan, C. L., Lin, Y. Y., Yang, Y. H., and Chen, H. C., “Effects of Rapid Thermal Annealing on Poly-Si TFT with Different Gate Oxide Thickness” , IEICE Transactions on Electronics, Vol. E93-C, No. 1, pp. 151-153 (2010)
[2.12]Bonnel, M., Duhamel, N., Haji, L., Loisel, B., and Stoemenos, J., “Polycrystalline Silicon Thin-Film Transistors with Two-step Annealing Process” , IEEE Electron Device Letters, Vol. 14, No. 12, pp. 551-553 (1991)
[2.13]Unagami, T., and Kogure, O., “Large On/Off Current Ratio and Low Leakage Current Poly-Si TFT’s with Multichannel Structure” , IEEE Transactions on Electron Devices, Vol. 35, No. 11, pp. 1986-1989 (1988)
[2.14]Song, I. H., Kim, C. H., Kang, S. H., Nam, W. J., and Han, M. K., “A New Multi-Channel Dual-Gate Poly-Si TFT Employing Excimer Laser Annealing Recrystallization on Pre-patterned a-Si Thin Film” , International Electron Devices Meeting Digest, pp. 561-564 (2002)
[2.15]Shieh, M. S., Sang, J. Y., Chen, C. Y., Wang, S. D., and Lei, T. F. “Electrical Characteristics and Reliability of Multi-channel Polycrystalline Silicon Thin-Film Transistors” , Japanese Journal of Applied Physics, Vol. 45, No. 4B, pp. 3159-3164 (2006)
[2.16]Levinson, J., Shepherd, F. R., Scanlon, P. J., Westwood, W. D., Este, G., and Rider, M., “Conductivity Behavior in Polycrystalline Semiconductor Thin Film Transistors” , Journal of Applied Physics, Vol. 53, No. 2, pp. 1193-1202 (1982)
[2.17]Proano, R. E., Misage, R. S., and Ast, D. G., “Development and Electrical Properties of Undoped Polycrystalline Silicon Thin-Film Transistors” , IEEE Transactions on Electron Devices, Vol. 36, No. 9, pp. 1915-1922 (1989)
[2.18]Chen, J. H., Lei, T. F., Chen, J. H., and Chao, T. S., “Characteristics of TEOS Polysilicon Oxides: Improvement by CMP and High Temperature RTA N2/N2O Annealing” , Journal of The Electrochemical Society, Vol. 147, No. 11, pp. 4282-4288 (2000)
[2.19]Kao, C. H., and Lai, C. S., “Performance and Reliability Improvements in Thin Film Transistors with Rapid Thermal N2O Annealing” , Semiconductor Science and Technology, Vol. 23, No. 2, p. 025020 (2008)
[2.20]Wu, Y. L., Wu, Z. Y., and Hwu, J. G., “Improvement in Reliability of n-MOSFETs by Using Rapid Thermal N2O-Reoxidized Nitrided Gate Oxides” , Solid-State Electronics, Vol. 38, No.4, pp. 839 -843 (1995)
[2.21]Yamauchi, N., Hajjar, J.J. J., and Reif, R., “Poly silicon Thin-Film Transistors with Channel Length and Width Comparable to or Smaller than the Grain Size of the Thin Film” , IEEE Transactions on Electron Devices, Vol. 38, No. 1, pp. 55-60 (1991)
[2.22]Chao, C. W., Wu, Sermon Y. C., Hu, G. R., and Feng, M. S., “Device Characteristics of Polysilicon Thin-Film Transistors Fabricated by Electroless Plating Ni-Induced Crystallization of Amorphous Si” , Japanese Journal of Applied Physics, Vol. 42, No. 4A, pp. 1556-1559 (2003)
[2.23]Hatalis, M. K., and Greve, D. W., “Large Grain Polycrystalline Silicon by Low Temperature Annealing of Low Pressure Chemical Vapor Deposited Amorphous Silicon Films” , Journal of Applied Physics, Vol. 63, No. 7, pp. 2260-2266 (1988)
[2.24]Noma, T., Yonehara, T., and Kumomi, H., “Crystal Forms by Solid-State Recrystallization of Amorphous Si Films On SiO2” , Applied Physics Letters, Vol. 59, No. 6, pp. 653-655 (1991)
[2.25]Yamauchi, N., Hajjar, J.-J.J., Reif, R., Nakazawa, K., and Tanaka, K., “Characteristics of Narrow-Channel Polysilicon Thin-Film Transistors” , IEEE Transactions on Electron Devices Vol. 38, No. 8, pp. 1967-1968 (1991)
[2.26]Zen, H. W., Chang, T. C., Shih, P. S., Peng, D. Z., Hwang, T. Y., and Chang, C. Y., “Analysis of Narrow Width Effect in Polycrystalline Silicon Thin Film Transistors” , Japanese Journal of Applied Physics, Vol. 42, No. 1, pp. 28-32 (2003)
[2.27]Yang, D. N., Fang, Y. K., Hwang, K. C., Lee, K. Y., Wu, K. H., Ho, J. J., Chen, C. Y., Wang, Y. J., Liang, M. S., Lee, J. Y., and Wuu, S. G., “Narrow Width Effects of Bottom-Gate Polysilicon Thin Film Transistors” , IEEE Electron Device Letters, Vol. 19, No. 11, pp. 429-431 (1998)

Chapter 3
[3.1]Tam, W. B., and Shimoda, T., “Modelling and Design of Polysilicon Drive Circuits for OLED Displays” , SID Symposium Digest of Technical Papers, Vol. 35, No. 1, pp. 1406-1409 (2004)
[3.2]Pribat, D., and Plais, F., “Low Temperature Polysilicon Technology for Active Matrix Addressing of LCDs and OLEDs” , Proceedings of SPIE, Vol. 4295, pp. 60-67 (2001)
[3.3]Olasupo, K. R., and Hatalis, M. K., “Leakage Current Mechanism in Sub-Micron Poly silicon Thin-Film Transistors” , IEEE Transactions on Electron Devices, Vol. 43, No. 8, pp. 1218-1223 (1996)
[3.4]Wright, P. J., and Saraswat, K. C., “The Effect of Fluorine in Silicon Dioxide Gate Dielectrics” , IEEE Transactions on Electron Devices, Vol. 36, No. 5, pp. 879-889 (1989)
[3.5]Fan, C. L., and Chen, M. C., “Performance Improvement of Excimer Laser Annealed Poly-Si TFTs Using Fluorine Ion Implantation” Electrochemical and Solid-State Letters, Vol. 5, No. 8, pp. G75-G77 (2002)
[3.6]Tsunoda, Y., Sameshima, T., and Higasha, S., “Improvement of Electrical Properties of Pulsed Laser Crystallized Silicon Films by Oxygen Plasma Treatment” , Japanese Journal of Applied Physics, Vol. 39, No. 4A, pp. 1656-1659 (2000)
[3.7]Hack, M., Lewis, A. G., and Wu, I.-W., “Physical Models for Degradation Effects in Polysilicon Thin-Film Transistors” , IEEE Transactions on Electron Devices, Vol. 40, No. 5, pp. 890-897 (1993)
[3.8]Lee, Y. S., Lin, H. Y., Lei, T. F., Huang, T. Y., Chang, T. C., and Chang, C. Y., “Comparison of N2 and NH3 Plasma Passivation Effects on Polycrystalline Silicon Thin-Film Transistors” , Japanese Journal of Applied Physics, Vol. 37, No. 7, pp. 3900-3903 (1998)
[3.9]Wang, F. S., Huang, C. Y., and Cheng, H. C., “Plasma Passivation Effects on Polycrystalline Silicon Thin-Film Transistors Utilizing Nitrous Oxide Plasma” , Japanese Journal of Applied Physics, Vol. 36, No. 4A, pp. 2028-2031 (1997)
[3.10]Yang, C. K., Lei, T. F., and Lee, C. L., “Characteristics of Top-Gate Thin-Film Transistors Fabricated on Nitrogen-Implanted Polysilicon Films” , IEEE Transactions on Electron Devices, Vol. 42, No. 12, pp. 2163-2169 (1995)
[3.11]Chang, C. W., Huang, P. W., Deng, C. K., Huang, J. J., Chang, H. R., and Lei, T. F., “CF4-Plasma-Induced Fluorine Passivation Effects on Poly-Si TFTs with High- Pr2O3 Gate Dielectric” , Journal of The Electrochemical Society, Vol. 155, No. 2, pp. J50-54 (2008)
[3.12]Fan, C. L., and Chen, M. C., “Effects of N2O Plasma Treatment on the Performance of Excimer-Laser-Annealed Polycrystalline Silicon Thin Film Transistors” , Japanese Journal of Applied Physics, Vol. 41, No. 9, pp. 5542-5545 (2002)
[3.13]Liang, G. T., and Hong, Franklin,C. N., “Diamond Growth by Hollow Cathode Arc Plasma Chemical Vapor Deposition” , Journal of Materials Research, Vol. 13, No. 11, pp. 3114-3121 (1998)
[3.14]Mildner, M., Korzec, D., and Engemann, J., “13.56 MHz Hollow Cathode Jet Matrix Plasma Source for Large Area Surface Coating” , Surface and Coatings Technology, Vol. 112, No. 1, pp. 366-372 (1999)
[3.15]Morimoto, Y., Jinno, Y., Hirai, K., Ogata, H., Yamada, T., and Yoneda, K., “Influence of the Grain Boundaries and Intragrain Defects on the Performance of Poly-Si Thin Film Transistors” , Journal of The Electrochemical Society, Vol. 144, No. 7, pp. 2495-2501 (1997)
[3.16]Dimitriadis, C. A., Coxon, P. A., Dozsa, L., Papadimitriou, L., and Economou, N., “Performance of Thin-Film Transistors on Polysilicon Films Grown by Low-Pressure Chemical Vapor Deposition at Various Pressures” , IEEE Transactions on Electron Devices, Vol. 39, NO. 3, pp. 598-606 (1992)
[3.17]Hack, M., Lewis, A. G., and Wu, I. W., “Physical Models for Degradation Effects in Polysilicon Thin-Film Transistors” , IEEE Transactions on Electron Devices, Vol. 40, No. 5, pp. 890-897 (1993)

Chapter 4
[4.1]Hseih, B. C., Hatalis, M. K., and Greve, D. W., “Low-Temperature Polycrystalline Silicon Thin-Film Transistors for Displays” , IEEE Transactions on Electron Devices, Vol. 35, No. 11, 1840-1845 (1988)
[4.2]Stewart, M., Howell, R. S., Pires, L., and Hatalis, M. K., “Polysilicon TFT Technology for Active Matrix OLED Displays” , IEEE Transactions on Electron Devices, Vol. 48, No. 5, pp. 845-851 (2001)
[4.3]Chang, K. M., Yang, W. C., and Tsai, C. P., “Electrical Characteristics of Low Temperature Polysilicon TFT with a Novel TEOS/Oxynitride Stack Gate Dielectric” , IEEE Electron Device Letters, Vol. 24, No. 8, pp. 512-514 (2003)
[4.4]Wu, I. W., Lewis, A. G., Huang, T. Y., and Chiang, A., “Passivation Kinetics of Two Types of Defects in Polysilicon TFT by Plasma Hydrogenation” , IEEE Electron Device Letters, Vol. 12, No. 4, pp. 181-183 (1991)
[4.5]Wang, F. S., Tsai, M. J., and Cheng, H. C., “The Effects of NH3 Plasma Passivation on Polysilicon Thin-Film Transistors” , IEEE Electron Device Letters, Vol. 16, No. 11, pp. 503-505 (1995)
[4.6]Fan, C. L., Lai, H. L., and Yang, T. H., “Enhanced Crystallization and Improved Reliability for Low-Temperature-Processed Poly-Si TFTs With NH3-Plasma Pretreatment Before Crystallization” , IEEE Electron Device Letters, Vol. 27, No. 7 pp. 756-578 (2006)
[4.7]Fan, C. L., Lai, H. L., and Chang, J. Y., “Improvement in Brightness Uniformity by Compensating for the Threshold Voltages of Both the Driving Thin-Film Transistor and the Organic Light-Emitting Diode for Active-Matrix Organic Light-Emitting Diode Displays” , Japanese Journal of Applied Physics Vol. 49, p. 05EB04 (2010)
[4.8]Kouvatsos, D. N., and Hatalis, M. K., “Polycrystalline Silicon Thin Film Transistors Fabricated at Reduced Thermal Budgets by Utilizing Fluorinated Gate Oxidation” , IEEE Transactions on Electron Devices, Vol. 43, No. 9, pp. 1448-1453 (1996)
[4.9]Tu, C. H., Chang, T. C., Liu, P. T., Chen, C. H., Yang, C. Y., Wu, Y. C., Liu, H. C., Chang, L. T., Tsai, C. C., Sze, Simon M., and Chang, C. Y., “Electrical Enhancement of Solid Phase Crystallized Poly-Si Thin-Film Transistors with Fluorine Ion Implantation” , Journal of The Electrochemical Society, Vol. 153, No. 9, pp. G815-G818 (2006)
[4.10]Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Wu, Y. H., Yang, T. Y., Kao, K. H., Chao, T. S., and Lei, T. F., “Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High-κ LTPS-TFT” , IEEE Electron Device Letters, Vol. 29, No. 2, pp. 168-170 (2008)
[4.11]Fan, C. L., and Chen, M. C., “Performance Improvement of Excimer Laser Annealed Poly-Si TFTs Using Fluorine Ion Implantation” , Electrochemical and Solid-State Letters, Vol. 5, No. 8, pp. G75-G77 (2002)
[4.12]Wang, S. D., Lo, W. H., and Lei, T. F., “CF4 Plasma Treatment for Fabricating High-Performance and Reliable Solid-Phase-Crystallized Poly-Si TFTs” , Journal of The Electrochemical Society, Vol. 152, No.9, pp. G703-G706 (2005)
[4.13]Chang, C. W., Huang, P. W., Deng, C. K., Huang, J. J., Chang, H. R., and Lei, T. F., “CF4-Plasma-Induced Fluorine Passivation Effects on Poly-Si TFTs with High-Pr2O3 Gate Dielectric” , Journal of The Electrochemical Society, Vol. 155, No. 2, pp. J50-J54 (2008)
[4.14]Levinson, J., Shepherd, F. R., Scanlon, P. J., Westwood, W. D., Este, G., and Rider, M., “Conductivity Behavior in Polycrystalline Semiconductor Thin Film Transistors” , Journal of Applied Physics, Vol. 53, No. 2, pp. 1193-1202 (1982)
[4.15]Proano, R. E., Misage, R. S., and Ast, D. G., “Development and Electrical Properties of Undoped Polycrystalline Silicon Thin-Film Transistors” , IEEE Transactions on Electron Devices, Vol. 36, No. 9, pp. 1915-1922 (1989)
[4.16]Olasupo, K. R., and Hatalis, M. K., “Leakage Current Mechanism in Sub-Micron Polysilicon Thin-Film Transistors” , IEEE Transactions on Electron Devices, Vol. 43, No. 8, pp. 1218-1223 (1996)
[4.17]Chang, C. P., and Wu, Sermon Y. C., “Effect of CF4 Plasma on Properties and Reliability of Metal-Induced Lateral Crystallization Silicon Transistors” , Journal of The Electrochemical Society, Vol. 157, No. 2 pp. H192-H195 (2010)
[4.18]Tu, C. H., Chang, T. C., Liu, P. T., Yang, C. Y., Liu, H. C., Chen, W. R., Wu, Y. C., and Chang, C. Y., “Improvement of Electrical Characteristics for Fluorine-Ion-Implanted Poly-Si TFTs Using ELC” , IEEE Electron Device Letters, Vol. 27, No. 4, pp. 262 (2006)
[4.19]Tu, C. H., Chang, T. C., Liu, P. T., Zan, H. W., Tai, Y. H., Yang, C. Y., Wu, Y. C., Liu, H. C., Chen, W. R., and Chang, C. Y., “Enhanced Performance of Poly-Si Thin Film Transistors Using Fluorine Ions Implantation” , Electrochemical and Solid-State Letters, Vol. 8, No. 9, pp. G246-G248 (2005)

Chapter 5
[5.1]Mimura, A., Konishi, N., Ono, K., Ohwada, J., Hosokawa, Y., Ono, Y. A., Suzuki, T., Miyata K., and Kawakami, H., “High Performance Low-Temperature Poly-Si n-Channel TFT’s for LCD” , IEEE Transactions on Electron Devices, Vol. 36, No. 2, pp. 351-359 (1989)
[5.2]Serikawa, T., Shirai, S., Okamoto, A., and Suyama, S., “Low-Temperature Fabrication of High-Mobility Poly-Si TFT’s for Large-Area LCD’s” , IEEE Transactions on Electron Devices, Vol. 36, No. 9 pp. 1929-1933 (1989)
[5.3]Olasupo, K. R., and Hatalis, M. K., “Leakage Current Mechanism in Sub-Micron Poly silicon Thin-Film Transistors” , IEEE Transactions on Electron Devices, Vol. 43, No. 8, pp. 1218-1223 (1996)
[5.4]Wu, I. W., Lewis, A. G., Huang, T. Y., and Chiang, A., “Passivation Kinetics of Two Types of Defects in Polysilicon TFT by Plasma Hydrogenation” , IEEE Electron Device Letters, Vol. 12, No. 4, pp. 181-183 (1991)
[5.5]Fan, C. L., and Chen, M. C., “Performance Improvement of Excimer Laser Annealed Poly-Si TFTs Using Fluorine Ion Implantation” , Electrochemical and Solid-State Letters, Vol. 5, No. 8, pp. G75-G77 (2002)
[5.6]Tsunoda, Y., Sameshima, T., and Higasha, S., “Improvement of Electrical Properties of Pulsed Laser Crystallized Silicon Films by Oxygen Plasma Treatment” , Japanese Journal of Applied Physics, Vol. 39, No. 4A, pp. 1656-1659 (2000)
[5.7]Chen, W. R., Chang, T. C., Liu, P. T., Wu, C. J., Tu, C. H., Sze, S. M., and Chang, C. Y., “Passivation Effect of Poly-Si Thin-Film Transistors With Fluorine-Ion-Implanted Spacers” , IEEE Electron Device Letters, Vol. 29, No. 6, pp. 603-605 (2008)
[5.8]Chang, C. W., Deng, C. K., Wu, S. C., Huang, J. J., Chang, H. R., and Lei, T. F., “Characterizing Fluorine-Ion Implant Effects on Poly-Si Thin-Film Transistors With Pr2O3 Gate Dielectric” , Journal of Display Technology, Vol. 4, No. 2, pp. 173-179 (2008)
[5.9]Matsumura, H., Nakagome, Y., and Furukawa, S., “A heatresisting new amorphous silicon” , Applied Physics Letters, Vol. 36, No. 6, pp. 439-440 (1980)
[5.10]Kim, C. H., Jeon, J. H., Yoo, J. S., Park, K. C., and Han, M. K., “Excimer-Laser-Induced In-Situ Fluorine Passivation Effects on Polycrystalline Silicon Thin Film Transistors” , Japanese Journal of Applied Physics, Vol. 38, No. 4B, pp. 2247-2250 (1999)
[5.11]Chang, C. W., Deng, C. K., Huang, J. J., Wang, T. Y., and Lei, T. F., “Electrical Enhancement of Polycrystalline Silicon Thin-Film Transistors Using Fluorinated Silicate Glass Passivation Layer” , Japanese Journal of Applied Physics, Vol. 47, No. 2, pp. 847-852 (2008)
[5.12]Miyajima, H., Katsumata, R., Nakasaki, Y., Nishiyama, Y., and Hayasaka, N., “Water Absorption Properties of Fluorine-Doped SiO2 Films Using Plasma-Enhance Chemical Vapor Deposition” , Japanese Journal of Applied Physics, Vol. 35, No. 12A pp. 6217-6225 (1996)
[5.13]Chang, W. J., Houng, M. P., and Wang, Y. H., “Fourier Transform Infrared Characterization of Moisture Absorption in SiOF Films” , Japanese Journal of Applied Physics, Vol. 38, No. 8, pp. 4642-4647 (1999)
[5.14]Tsai, M. Y., Streetman, B. G., Williams, P., and Evans, Jr. C. A., “Anomalous Migration of Fluorine and Electrical Activation of Boron in BF+2 Implanted Silicon” , Applied Physics Letters, Vol. 32, No. 3, pp. 144-147 (1978)
[5.15]Levinson, J., Shepherd, F. R., Scanlon, P. J., Westwood, W. D., Este, G., and Rider, M., “Conductivity Behavior in Polycrystalline Semiconductor Thin Film Transistors” , Journal of Applied Physics, Vol. 53, No. 2, pp. 1193-1202 (1982)
[5.16]Proano, R. E., Misage, R. S., and Ast, D. G., “Development and Electrical Properties of Undoped Polycrystalline Silicon Thin-Film Transistors” , IEEE Transactions on Electron Devices, Vol. 36, No. 9, pp. 1915-1922 (1989)

Chapter 6
[6.1]Hosokawa, C., Matsuura, M., Eida, M., Fukuoka, K., Tokailin, H., and Kusumoto, T., “Full-Color Organic EL Display” , SID Symposium Digest of Technical Papers, Vol. 29, No. 1, pp. 7-10 (1998)
[6.2]Lin, C. W., Pang, D. Z., Lee, R., Shih, Y. F., Jan, C. K., Hsieh, M. H., Chang, S. C., and Tsai, Y. M., Proc. Int. Symp. International Display Manufacturing Conference and Exhibition, 2005, p. 315.
[6.3]Dawson, R. M. A., Shen, Z., Furst, D. A., Connor, S., Hsu, J., Kane, M. G., Stewart, R. G., and Ping, K., “The Impact of the Transient Response of Organic Light Emitting Diodes on the Design of Active Matrix OLED Displays” , Proceedings of International Symposium Technical Digest International Electron Devices Meeting, pp. 875-878 (1998)
[6.4]Kimura, M., Yudasaka, I., Kanbe, S., Kobayashi, H., Kiguchi, H., Seki, S. I., Miyashita, S., and Ohshima, H., “Low-Temperature Polysilicon Thin-Film Transistor Driving with Integrated Driver for High-Resolution Light Emitting Polymer Display” , IEEE Transactions on Electron Devices, Vol. 46, No. 12, pp. 2282-2288 (1999)
[6.5]Lee, J. H., You, B. H., Nam, W. J., Lee, H. J., and Han., M. K., “A New a-Si:H TFT Pixel Design Compensating Threshold Voltage Degradation of TFT and OLED” , SID Symposium Digest of Technical Papers, Vol. 35, No. 1 pp. 264-267 (2004)
[6.6]Choi, S. M., Kwon, O. K., and Chung, H. K., “An Improved Voltage Programmed Pixel Structure for Large Size and High Resolution AM-OLED Displays” , SID Symposium Digest of Technical Papers, Vol. 35, No. 1 pp. 260-263 (2004)
[6.7]Lu, H. Y., Liu, P. T., Chang, T. C., and Chi, S., “Enhancement of Brightness Uniformity by a New Voltage-Modulated Pixel Design for AMOLED Displays” , IEEE Electron Device Letters Vol. 27, No. 9 pp. 743-745 (2006)
[6.8]Lee, J. H., Park, S. G., Jeno, J. H., Goh, J. C., Huh, J. M., Choi, J., Chung, K., and Han, M. K., “New Fraction Time Annealing Method For Improving Organic Light Emitting Diode Current Stability of Hydorgenated Amorphous Silicon Thin-Film Transistor Based Active Matrix Organic Light Emitting Didode Backplane” , Japanese Journal of Applied Physics, Vol. 46, No. 3B, pp. 1350-1353 (2007)
[6.9]Shin, H. S., Lee, W. K., Park, S. G., Kuk, S. H., and Han, M. K., “Active-Matrix Organic Light Emission Diode Pixel Circuit for Suppressing and Compensating for the Threshold Voltage Degradation of Hydrogenated Amorphous Silicon Thin Film Transistors” , Japanese Journal of Applied Physics, Vol. 48 p. 03B023 (2009)
[6.10]Lee, J. H., Nam, W. J., Jung, S. H., and Han. M. K., “A new current scaling pixel circuit for AMOLED” , IEEE Electron Device Letter, Vol. 25, No. 5, pp. 280-282 (2004)
[6.11]He, Y., Hattori, R., and Kanicki, J., “Four-Thin Film Transistor Pixel Electrode Circuits for Active-Matrix Organic Light-Emitting Displays” , Japanese Journal of Applied Physics, Vol. 40, No. 3A, pp. 1199-1208 (2001)
[6.12]Lee, J. H., Nam, W. J., Kim, C. Y., Shin, H. S., Kim, C. D., and Han, M. K., “New Current-Scaling Pixel Circuit Compensating Non uniform Electrical Characteristics for Active Matrix Organic Light Emitting Diode” , Japanese Journal of Applied Physics, Vol. 45, No. 5B, pp. 4402-4406 (2006)
[6.13]Lee, H., Yoo, J. S., Kim, C. D., Chung, I. J., and Kanicki, J., “Novel Current-Scaling Current-Mirror Hydrogenated Amorphous Silicon Thin-Film Transistor Pixel Electrode Circuit with Cascade Capacitor for Active-Matrix Organic Light-Emitting Devices” , Japanese Journal of Applied Physics, Vol. 46, No. 3B, pp. 1343-1349 (2007)
[6.14]Mizukami, M., 6-Bit Digital VGA OLED” , SID Symposium Digest of Technical Papers, Vol. 31, No.1, pp. 912-915 (2000)
[6.15]Kang, M. H., Hur, J. H., Nam, Y. D., Lee, E. H., Kim, S. H., and Jang, J., “An Optical Feedback Compensation Circuit With a-Si:H Thin-Film Transistors for Active Matrix Organic Light Emitting Diodes” , Journal of Non-Crystalline Solids, Vol. 354, pp. 2523-2528 (2008)
[6.16]Lin, Y. C., and Shsieh. H. P. D., “Improvement of Brightness Uniformity by AC Driving Scheme for AMOLED Display” , IEEE Electron Device Letter, Vol. 25, No. 11, pp. 728-730 (2004)
[6.17]Lee, J. H., Park, S. G., Han, S. M., and Park, K. C., “New PMOS LTPS–TFT Pixel for AMOLED to Suppress the Hysteresis Effect on OLED Current by Employing a Reset Voltage Driving” , Solid-State Electronics, Vol. 52, No. 3, pp. 462-466 (2008)
[6.18]Chen, B. T., Tai, Y. H., Kuo, Y. J., Tsai, C. C., and Cheng, H. C., “New Pixel Circuits for Driving Active Matrix Organic Light Emitting Diodes” , Solid-State Electronics, Vol. 50, No. 50, pp. 272-275 (2006)
[6.19]Fish, D., Young, N., Deane, S., Steer, A., George, D., Giraldo, A., Lifka, H., Gielkens, O., and Oepts, W., “Optical Feedback for AMOLED Display Compensation using LTPS and a-Si:H Technologies” , SID Symposium Digest of Technical Papers, Vol. 36, No. 38, pp. 1340-1343 (2005)
[6.20]Torres, D. A., Lister, P. F., and Newbury, P., “LUT-based Compensation Model for OLED Degradation” , Journal of the Society for Information Display, Vol. 13, No. 5, pp. 435-441 (2005)
[6.21]Lee, J. H., Kim, J. H., and Han, M. K., “A new a-Si:H TFT Pixel Circuit Compensating the Threshold Voltage Shift of a-Si:H TFT and OLED for Active Matrix OLED” , IEEE Electron Device Letters, Vol. 26, No. 12, pp. 897-899 (2005)
[6.22]Ashtiani, S. J., Chaji, G. R., and Nathan, A., “AMOLED Pixel Circuit With Electronic Compensation of Luminance Degradation” , Journal of Display Technology, Vol. 3, No. 1, pp. 36-39 (2007)
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