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研究生:張珈瑋
研究生(外文):Chia-Wei Chang
論文名稱:新型互補式金氧半注入鎖定除頻器與倍頻器之設計
論文名稱(外文):Design of Novel CMOS Injection Locked Frequency Dividers and Frequency multipliers
指導教授:張勝良
指導教授(外文):Sheng-Lyang Jang
口試委員:張勝良
口試日期:2012-06-25
學位類別:博士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:168
中文關鍵詞:電壓控制振盪器除三注入鎖定除頻器除四注入鎖定除頻器注入鎖定倍頻器
外文關鍵詞:VCOdivide-by-3 ILFDdivide-by-4 ILFDinjection-locked frequency multiplier
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電壓控制振盪器與除頻器是頻率合成器電路中,主要的電路之一。對電壓控制振盪器而言,低相位雜訊可避免相鄰雜訊訊號經由混波轉換的干擾。而振盪器的輸出則經由除頻器來達成降頻的工作,因此,除頻器需具有高頻操作,寬的操作頻寬及低功率消耗。
在這篇論文我們先提出三個差動LC-tank電壓控制振盪器,成功的在0.13 μm CMOS製程實現;首先我們設計兩個考畢子電壓控制振盪器,電路架構是一個偏壓閘極洩極的全NMOS LC-tank電壓控制振盪器,並使用洩極與基底短路的MOSFET來降低功耗。接著我們還提出一個使用串聯式共振腔的電壓控制振盪器,電源電壓為0.8 V時,電壓控制振盪器輸出之相位雜訊在距離載波頻率(20.57 GHz)1 MHz處所量測之結果為-110.28 dBc/Hz。
注入鎖定技術可達到高頻操作及低功率損耗的功能。基於此技術,呈現三個除三注入鎖定除頻器與三個除四注入鎖定除頻器,並具寬注入鎖定除頻範圍之應用。首先我們提出一個寬注入鎖定除頻範圍與寬工作範圍的注入鎖定除頻器,這個除三注入鎖定除頻器使用非線性混波HBT和主動電感架構,具有寬的注入鎖定除頻範圍;由於使用HBT變容器有寬可調範圍,故本電路具有寬的工作範圍;在注入功率為0 dBm時,除三工作範圍為9.3 GHz (7.1 GHz ~ 16.4 GHz)。接著我們提出了一個使用90 nm CMOS製程的寬注入鎖定範圍除三注入鎖定除頻器,這個除頻器包含了NMOSFETs交錯耦合P型阿姆斯壯LC振盪器和中心抽頭電感連接PMOSFETs架構,這個PMOSFETs架構可實現成一個線性和二次諧波混波器,在注入功率為0 dBm時,注入鎖定除頻範圍為4.28 GHz(19.8%),從19.52 GHz至 23.8 GHz。最後我們提出一個寬注入鎖定除頻範圍的主動電感除三注入鎖定除頻器,我們使用雙推式交錯耦合n型MOS LC-tank振盪器來實現這個注入鎖定除頻器,在注入功率為0 dBm時,工作範圍為5.9 GHz(80.27%),從4.4 GHz至10.3 GHz。
我們設計一個除四注入鎖定除頻器,使用主動電感來增加可調範圍,另外使用電晶體組成的兩個線性混波器結構來增加注入鎖定除頻範圍,在注入功率為0 dBm時,工作範圍為5.8 GHz(89.2%),從3.6 GHz至9.4 GHz。接著我們設計了一個低電壓、寬注入鎖定除頻範圍與寬工作範圍的除四注入鎖定除頻器,這個除頻器使用了並聯式共振腔電壓控制振盪器和使用三個電晶體組成的注入元件,其注入元件具有線性與非線性之功能,在注入功率為0 dBm時,工作範圍為5.3 GHz(22.31%),從21.1 GHz至26.4 GHz。最後我們提出一個使用主動電感電壓控制振盪器設計的除四注入鎖定除頻器,使用了三個電晶體組成的注入元件,其注入元件包含兩個NMOSFETs與一個PMOSFET來達到線性與非線性混波器的功能,在注入功率為0 dBm時,工作範圍為2.3 GHz (14.7%),從14.5 GHz至16.8 GHz。
頻率倍頻方式的優點為可以讓振盪器使用廉價製程技術產生高的頻率輸出,設計振盪器在較低的頻率可有高品質因素的可變電容,故我們設計注入鎖定倍頻器電路,本論文將敘述三個使用CMOS製程實現的注入鎖定倍頻器。首先我們提出一個使用0.18 μm CMOS 製程實現之LC-tank注入鎖定倍頻器,這個電路是由一個頻率倍頻器、第一諧波注入鎖定振盪器、變壓器分波器組成,第一諧波注入鎖定振盪器會放大及鎖定頻率倍頻器的輸出訊號,並濾掉其他不要的訊號,在注入功率為0 dBm時,輸入工作範圍為3.78 GHz至4.52 GHz,輸出頻率為7.56 GHz至9.04 GHz。接著我們提出一個使用0.18 μm CMOS 製程實現之雙共振腔CMOS LC-tank注入鎖定倍頻器,這個倍頻器是由一個寬頻帶頻率倍頻器、雙共振腔第一諧波注入鎖定振盪器、變壓器分波器組成,在注入功率為0 dBm時,高頻帶/低頻帶輸入工作範圍為3.9/1.7 GHz至6.1/2 GHz,輸出頻率為7.8/3.4 GHz至12.2/4 GHz。最後我們設計一個注入鎖定四倍頻器,注入鎖定四倍頻器包含了兩個頻率倍頻器、第一諧波注入鎖定振盪器、變壓器分波器組成,在注入功率為0 dBm時,輸入工作範圍為6 GHz至7.4 GHz,輸出頻率為24 GHz至29.6 GHz。
The key building blocks in the frequency synthesizer are the voltage controlled oscillator (VCO) and the high frequency divider circuit. Most importantly, low phase-noise is required to avoid corrupting the mixer-converted signal by close interfering tones for VCO circuit. The output of the VCO is divided down by the frequency divider which requires operating at high frequencies, wide operating range and lower power consumption.
First, this thesis describes three differential LC-tank voltage controlled oscillators and successfully implemented in the 0.13 μm CMOS process. Two differential Colpitts voltage-controlled oscillators (VCOs) are designed. The circuit topology is an all NMOS LC-tank VCO with gate and drain dc biases, and a drain-connected–to-body MOSFET is used to lower the power consumption. We proposed a VCO circuit using series-tuned resonator. At the supply voltage of 0.8 V, the output phase noise of the VCO is -110.28 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 20.57 GHz.
The injection locking technique is applied in high speed, low power frequency dividers, namely injection locked frequency dividers (ILFDs). Based on this technique, three divide-by-3 ILFDs and three divide-by-4 ILFDs are presented for wide locking range application. We proposed a wide locking range and operation range injection locked frequency divider. The active-inductor divide-by-3 ILFD has wide locking range due to the use of nonlinear mixer HBTs and active inductor, and has wide operation range due to the use of HBT varactor to extend the tuning range. At the incident power of 0 dBm the divide-by-3 operation range is 9.3 GHz, continuously from the incident frequency 7.1 GHz to 16.4 GHz. A wide-locking range divide-by-3 injection-locked frequency divider fabricated in the 90 nm 1P9M CMOS technology. The divider consists of an NMOS cross-coupled p-core Armstrong LC oscillator and a center-tapped inductor in series with the PMOSFETs. The PMOSFETs are used as a linear and second harmonic mixer. At the incident power of 0 dBm, the locking range is 4.28 GHz (19.8%), from the incident frequency 19.52 to 23.8 GHz. A new wide locking range active-inductor divide-by-3 injection-locked frequency divider is presented. The push-push ILFD circuit is realized with a push-push cross-coupled n-core MOS LC-tank oscillator. At the incident power of 0 dBm, the operation range is 5.9 GHz (80.27%), from 4.4 GHz to 10.3 GHz.
A divide-by-4 ILFD uses an active inductor to increase the tuning range and a transistor composite to serve an injection device with two linear mixers to enhance the locking range of ILFD. At the incident power of 0 dBm, the operation range of the divide-by-4 is about 5.8 GHz, from the incident frequency 3.6 GHz to 9.4 GHz, the percentage is 89.2%. A low voltage, wide locking range and operation range divide-by-4 injection-locked frequency divider (ILFD) is proposed. The divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with a parallel-tuned LC resonator and a three-transistor composite to serve as an injection device with the function of linear and nonlinear mixers. At the incident power of 0 dBm the operation range of the divide-by-4 is 5.3 GHz, from the incident frequency 21.1 GHz to 26.4 GHz, the percentage is 22.31%. A divide-by-4 ILFD uses a cross-coupled voltage-controlled oscillator (VCO) with an active inductor and a three-transistor composite consisted of two NMOSFETs and one PMOSFET to serve as an injection device with the function of linear and nonlinear mixers. At the incident power of 0 dBm the operation range of the divide-by-4 is 2.3 GHz, from the incident frequency 14.5 GHz to 16.8 GHz, the percentage is 14.7%.
Finally, the frequency multiplication approach offers the advantage that the oscillator can be fabricated in low cost silicon technology for high frequency generation. Injection-locked frequency multipliers allow the design of oscillators running at a frequency lower than required to take the advantage of higher Q-factor varactor. This thesis describes three injection-locked frequency multipliers and successfully implemented in the CMOS process. We propose a CMOS LC-tank injection locked frequency doubler (ILFD) fabricated in 0.18 μm CMOS process. The differential input and output ILFD circuit is realized with a frequency doubler, a first-harmonic injection-locked oscillator (ILO), and a transformer balun. The first-harmonic ILO amplifies the 2nd harmonic generated by the frequency doubler and filters out other undesired signals. At the incident power of 0dBm, the locking range is from the incident frequency 3.78 to 4.52 GHz. The output frequency is from 7.56 to 9.04 GHz. We propose a dual-resonance CMOS LC-tank injection locked frequency doubler (ILFD) fabricated in the 0.18 μm CMOS process. The ILFD circuit is composed of a dual-resonance first-harmonic injection-locked oscillator (ILO) with dual-injection ports, a wide-band frequency doubler and a transformer balun. At the incident power of 0 dBm, the ILFD has high/low operation range from the incident frequency 3.9/1.7 GHz to 6.1/2 GHz to provide a dual-band signal source with the frequency 7.8/3.4 GHz to 12.2/4 GHz. We designed a CMOS LC-tank injection locked frequency quadrupler. The injection-locked frequency quadrupler comprises a first-harmonic injection-locked oscillator with dual-injection ports, two frequency doublers and a transformer balun. At the incident power of 0 dBm, the injection-locked frequency quadrupler can provide an output signal with the frequency from 24 GHz to 29.6 GHz, while the frequency of the injection signal varies from 6 GHz to 7.4 GHz.
中文摘要 I
Abstract IV
誌 謝 VII
Table of Contents VIII
List of Figures XI
List of Tables XVII
Chapter 1 Introduction 1
1.1 Background 1
1.2 Thesis organization 4
Chapter 2 Overviews of Voltage-Controlled Oscillators and Injection-Locked Frequency Divider 5
2.1 The Oscillator 5
2.1.1 Negative Resistance (NR) 5
2.1.2 Positive Feedback (PFB) 8
2.2 All Types of Oscillators 9
2.2.1 Ring Oscillator 10
2.2.2 LC-Tank Oscillator 13
2.3 Voltage-Controlled Oscillator 15
2.4 The Parameters of VCOs 16
2.4.1 Center Frequency 16
2.4.2 Tuning Range 17
2.4.3 Tuning Linearity 18
2.4.4 Output Amplitude 18
2.4.5 Power Dissipation 19
2.4.6 Supply and Common-Mode Rejection 19
2.4.7 Output Signal Purity 19
2.5 Phase noise 19
2.5.1 Definition of Phase Noise 20
2.5.2 Existing Models of Phase Noise 22
2.5.2.1 Time-invariant phase noise model 22
2.5.3 Noise Sources 24
2.5.3.1 Thermal noise 24
2.5.3.2 Flicker noise 26
2.5.4 Phase Noise in Wireless Communication 28
2.5.5 Previous Models of Phase Noise 30
2.6 On-Chip Inductor Research 31
2.7 Varactor 39
2.7.1 P-N Junction Varactor 39
2.7.2 MOS Varactor 40
2.7.2.1 Accumulation-mode MOS varactor 41
2.7.2.2 Inversion-mode MOS varactor 43
2.8 Resistors 45
2.9 Injection Locking 46
Chapter 3 Design of Voltage-Controlled Oscillators 51
3.1 A Differential VCO Using the Drain-Connected-to-Body MOSFET 52
3.1.1 Design of A Differential VCO 54
3.1.2 Measurement and Discussion 56
3.2 A Low-Voltage Differential VCO in 0.13 μm CMOS Process 59
3.2.1 Design of Differential Colpitts VCO 60
3.2.2 Measurement and Discussion 63
3.3 A 21 GHz Series-Tuned VCO in 0.13μm CMOS Technology 66
3.3.1 Circuit Design 68
3.3.2 measurement results 70
3.4 Summary 73
Chapter 4 Design of Divide-by-3 Injection-Locked Frequency Divider 75
4.1 Low-Power Wide Operation Range SiGe HBT Injection Locked Frequency Divider 76
4.1.1 Design of A Low-Power Wide Operation Range ILFD 76
4.1.2 Measurement And Discussion 81
4.2 A 90nm CMOS LC-tank Divide-by-3 Injection-locked Frequency Divider with Record Locking Range 84
4.2.1 Circuit Design 84
4.2.2 Measurement Results 87
4.3 Wide locking Range ÷3 Active Inductor ILFD Using the Push-Push Oscillator 90
4.3.1 Design of The Wide locking Range ÷3 ILFD 91
4.3.2 Measurement Results 92
4.4 Summary 96
Chapter 5 Design of Divide-by-4 Injection-Locked Frequency Divider 98
5.1 Divide-by-4 Injection-Locked Frequency Divider Using Two Linear Mixers 98
5.1.1 Circuit Design 99
5.1.2 Measurement Results 102
5.2 LC Divide-by-4 ILFD Using the 2nd Harmonic Feedback 105
5.2.1 Design of The LC Divide-by-4 ILFD 105
5.2.2 Measurement and discussion 108
5.3 A Differential BiCMOS Divide-by-4 Injection-Locked Frequency Divider 112
5.3.1 Circuit Design 112
5.3.2 Measurement Results 115
5.4 Summary 119
Chapter 6 Design of Injection-Locked Frequency Doubler and Frequency Quadrupler 121
6.1 A Differential Input/Output Injection-Locked Frequency Doubler in 0.18μm CMOS Technology 122
6.1.1 Design of The Injection-Locked Frequency Doubler 123
6.1.2 Measurement Results 127
6.2 A Dual-Resonance Injection-Locked Frequency Doubler in 0.18μm CMOS Technology 135
6.2.1 Circuit Design 135
6.2.2 Measurement Results 138
6.3 An Injection-Locked Frequency Quadrupler in 90nm CMOS Technology 141
6.3.1 Circuit Design 142
6.3.2 Measurement Results 144
6.4 Summary 148
Chapter 7 Conclusions 149
References 154
Publications 162
Author’s Brief Introduction 168
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