(3.236.231.14) 您好!臺灣時間:2021/04/14 02:01
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:李偉豪
研究生(外文):Wei-Hao Lee
論文名稱:高效能串聯調諧交叉耦合壓控振盪器與雙頻帶注入鎖定除頻器之設計
論文名稱(外文):Design of High-performance Series-Tuned Cross-Coupled Voltage-Controlled Oscillator and Dual Band Injection-Locked Frequency Divider
指導教授:張勝良
指導教授(外文):Sheng-Lyang Jang
口試委員:張勝良
口試日期:2012-07-18
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:100
中文關鍵詞:除頻器壓控振盪器雙共振腔串聯共振
外文關鍵詞:dividervcodual bandseries tuned
相關次數:
  • 被引用被引用:0
  • 點閱點閱:47
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
首先,本論文提出一個只使用電源電壓和可調電壓的低相位雜訊新型互補式哈特萊壓控振盪器,此低雜訊 CMOS VCO是使用台積電0.18微米一般製程。此VCO操作在5.49 GHz到6.29 GHz ,可調範圍約為13.58%。量測雜訊在距離工作頻率5.65 GHz 1MHz的地方為-118.42 dBc/Hz。此VCO的消耗功率為1.694 mW。此晶片面積為0.529 × 0.674 mm2且其F.O.M為-191.09 dBc/Hz。 在電源電壓1.1V ,電流1.54 mA此功耗為1.694 mW。
其次,我們介紹一個新型雙共振除三注入鎖定除頻器。此雙共振LC共振腔包含了一個並聯LC共振腔和一個串連LC共振腔串連起來。此ILFD使用台積電0.18微米一般製程且功耗為3.93 mW在直流偏壓為0.65 V時。在注入能量0 dbm時低頻段和高頻段的除三鎖定範圍各自從8.6 GHz到9.4 GHz(8.79 %)以及16.6 GHz到17.4 GHz( 4.11 %)。
最後,我們呈現一個使用series-tuned的新型四相位壓控振盪器。此四相位壓控振盪器包含兩個底端串聯耦合的交叉耦合對VCO。在供給電壓為0.7 V時功耗為2.8 mW。當可調電壓從0到1.1 V時頻率從6.68 GHz到7.64 GHz其可調範圍為13.35 %。此四相位壓控振盪器是使用台積電0.18微米一般製程且其晶片面積為0.854 × 0.854 mm2。量測雜訊在距離工作頻率5.65 GHz 1MHz的地方為-118.23 dBc/Hz且此四相位壓控振盪器F.O.M為-191.39 dBc/Hz。
First, this thesis presents a novel complementary low phase noise differential CMOS Hartley voltage-controlled oscillator (VCO), which uses only the supply voltage and the tuning voltage as the biases. The low noise CMOS VCO has been implemented with the TSMC 0.18 um 1P6M polycide CMOS technology. The VCO operates from 5.49 GHz to 6.29 GHz with 13.58 % tuning range. The measured phase noise at 1-MHz offset is -118.42 dBc/Hz at 5.65 GHz. The power consumption of the VCO core is 1.694 mW. The VCO occupies a chip area of 0.529 ×0.674 mm2 and provides a figure of merit of -191.09 dBc/Hz. At the supply voltage of 1.1V, the core current of 1.54 mA, the core power consumption is 1.694 mW.
Secondly, we introduce the operation principle and design of a novel differential dual-resonance divide-by-3 injection-locked frequency divider (ILFD). The dual-resonance LC resonator is consisted of a parallel-tuned LC resonator in shunt with a series resonant LC tank. The ILFD was implemented with the TSMC 0.18 μm 1P6M CMOS technology and the core power consumption is 3.93 mW at the dc drain-source bias of 0.65 V. At the input power of 0 dBm, the low-frequency band and high-frequency band divide-by-3 locking ranges are respectively from 8.6 GHz to 9.4 GHz (8.79 %) and 16.6 GHz to 17.4 GHz (4.11 %).
Finally, we presents a new quadrature cross-coupled voltage-controlled oscillator (QVCO) using a series-tuned resonator. The LC-tank QVCO consists of two bottom-series coupled differential cross-coupled VCOs. At the supply voltage of 0.7 V, the total power consumption is 2.8 mW. The free-running frequency tuning range is 13.35%, tunable from 6.68 GHz to 7.64 GHz as the tuning voltage is varied from 0.0 V to 1.1 V. The QVCO has been implemented with the TSMC 0.18 μm CMOS technology and the die area is 0.854 × 0.854 mm2. The measured phase noise at 1 MHz offset is -118.23 dBc/Hz at the oscillation frequency of 6.81 GHz and the figure of merit (FOM) of the proposed QVCO is about -190.39 dBc/Hz.
Abstract III
誌謝 V
Table of Contents VI
List of Figures VIII
List of Tables XI
Chapter 1 Introduction 1
1.1 Background 1
1.2 Research Motivation 3
1.3 Framework of the Thesis 4
Chapter 2 Principles and Design Concepts of Voltage-Controlled Oscillators 6
2.1 Performance Parameters 6
2.2 Basic Principles of Oscillators 10
2.2.1 Feedback (Two-Port) Oscillators 11
2.2.2 Negative Resistance 13
2.3 Categorization of Oscillators 15
2.3.1 Ring Oscillator 15
2.3.2 LC-Tank Oscillator 17
2.4 Overview of the Cross-Coupled Oscillator 23
2.5 Voltage-Controlled Oscillators 27
2.6 Phase Noise and Q factor in Oscillators 28
2.6.1 Linear Time Invariant (LTI) Model - (The Lesson’s model) 30
2.6.2 Linear Time Variant (LTV) Model - (The Hajimiri’s Model) 34
2.6.3 Kinds of Noise 40
2.6.4 Phase Noise in Wireless Communications 43
2.6.5 Quality Factor 46
2.7 Quadrature Oscillators 48
2.8 Appearance of Dual-Resonantce 54
2.8.1 Dual-Band Resonator 54
2.8.2 Two Series-LC Resonators 58
Chapter 3 Principles and Design Concepts of Injection Locking Frequency Divider 59
3.1 Principle of Injection Locked Frequency Divider 60
3.2 Locking Range 62
3.3 Direct ILFD 65
Chapter 4 A Differential Complementary Hartley CMOS Voltage Controlled Oscillator 66
4.1 Introduction 66
4.2 Circuit Design 68
4.3 Measurement Results 70
Chapter 5 Differential Divide-by-3 Dual-Resonance Injection-Locked
Frequency Divider 74
5.1 Introduction 74
5.2 Circuit Design 76
5.3 Measurement Results 81
Chapter 6 A Series-Tuned Quadrature Cross-Coupled VCO In 0.18 μm CMOS 86
6.1 Introduction 86
6.2 Circuit Design 87
6.3 Measurement Results 90
Chapter 7 Conclusion 94
References 96
[1]I.R. Chamas and S. Raman, “A 5 GHz I/Q Phase-tunable CMOS LC Quadrature VCO (PT-QVCO) for Analog Phase Calibrated Receiver Architectures,” Silicon Monolithic Integrated Circuits in RF Systems, 2007 Topical Meeting on 10-12 Jan. 2007 Page(s):269 - 272
[2]B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
[3]D. Hauspie, E.-C. Park, and J. Craninckx, “Wide-band VCO with simultaneous switching of frequency band, active core, and varactor size,” IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1472–1480, Jul. 2007.
[4]J. Tang and D. Kasperkovitz, Oscillator Design Efficiency: A New Figure Of Merit For Oscillator Benchmarking.
[5]N. M. Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuit, vol. 27, no. 5, pp. 810–820, May 1992.
[6]B.Razavi, RF Microelectronics, Prentice Hall PTR 1998.
[7]S. –Jun. Lee, B. Kim, K. Lee, “A Novel High-Speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed Delay Scheme,” IEEE Journal of Solid-State Circuits, vol. 32, No. 2, February 1997.
[8]Behzad Razavi Design of Integrated Circuits for Optical Communications, Mc Graw Hill.
[9]劉隽宇, 翁若敏, “運用於IEEE 802.11a CMOS 頻率合成器的低雜訊寬調變範圍之壓控振盪器,” 2005.07.
[10]林曉彤, 莊惠如, “應用於無線通訊之CMOS 射頻微機電開關及2-GHz/5-GHz 壓控振盪器RFIC之研究” 2004.06.
[11]John Starr Hamel “LC tank Voltage Controlled Oscillator Tutorial,” Waterloo, Ontario, Canade, 2005
[12]D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, no. 2, pp. 329–330, Feb. 1966
[13]A. Hajimiri and T. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
[14]T. H. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuit, vol. 35, no. 3, pp. 326–336, Mar. 2000.
[15]T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press 1998.
[16]J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
[17]Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS
circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
[18]J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-um CMOS
technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
[19]H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency
dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
[20]H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
[21]M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in
0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
[22]H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
[23]R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
[24]P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking
Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
[25]W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
[26]H. Wu, “Signal generation and processing in high-frequency/high-speed
silicon-based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[27]R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973.
[28] A. Hajimiri and T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717–724, May 1999.
[29]R. Aparicio and A. Hajimiri, “A noise-shifting differential Colpitts VCO,” IEEE J. Solid-State Circuits, vol. 12, no. 12, pp. 1728–1736, Dec. 2002.
[30]S.-H. Lee, Y.-H. Chuang, S.-L. Jang and C.-C. Chen, ” Low-phase noise Hartley differential CMOS voltage controlled oscillator,” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 2, pp. 145-147, Feb. 2007.
[31]S.-L. Jang, Che Yi Lin, C.-F. Lee, and M.-H. Juang,” A complementary Hartley injection-locked frequency divider,” Micro. and Opti. Tech. Lett., vol. 49, no. 11, pp.2817-2820, Nov. 2007.
[32]S.-L. Jang, C.-Y. Wu, C.-C. Liu, and M.-H. Juang, ” A 5.6 GHz low power balanced VCO in 0.18 μm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 4, pp. 233-235, April, 2009.
[33]Y.-H. Chuang, S.-L. Jang, S.-H. Lee, R.-H. Yen and J.-J. Jhao, “5 GHz low power CMOS differential Armstrong VCOs with balanced current-reused topology , ” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 2, pp. 139-141, Feb. 2007.
[34]S.-L. Jang, C.-C. Liu, Y.-J. Song, and M.-H. Juang , ” A low voltage balanced Clapp VCO in 0.13 μm CMOS technology,” Micro. and Opti. Tech. Lett., vol. 52, no. 7, pp., 1623-1625, July, 2010.
[35]C. Cha and S. Lee, “A complementary colpitts oscillator in CMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 881–887, Mar. 2005.
[36]M.-D. Tsai, Y.-H. Cho, and H. Wang, J. Park, J. Park, Y. Choi, K. Sim, and D. Baek, “A fully-differential complementary Hartley VCO in 0.18 μm CMOS Technology,” IEEE Microwave Wireless Compon. Lett., vol. 20, no 2, pp. 91-93, 2011.
[37]G. De Astis, D. Cordeau, J.-M. Paillot, L. Dascalescu, “A 5-GHz fully integrated full PMOS low-phase-noise LC VCO,” IEEE J. Solid-State Circuits, vol. 40, Issue 10, pp.2087-2091, Oct. 2005.
[38]M.-D. Tsai, Y.-H. Cho, and H. Wang, “A 5-GHz low phase noise differential Colpitts CMOS VCO,” IEEE Microwave Wireless Compon. Lett., vol. 15, no 5, pp. 327-329, May 2005.
[39]C. M. Hung, B. Floyd, and K. K. O, “A fully integrated 5.35-GHz CMOS VCO and a prescaler,” IEEE Trans. Microwave Theory Tech., vol. 49, no. 1, pp. 17–22, Jan. 2001.
[40]A. Jerng, C. G. Sodini, “The impact of device type and sizing on phase noise mechanisms,” IEEE J. Solid-State Circuits, vol. 40, Issue 10, pp. 360-369, Feb. 2005.
[41]S.-L. Jang, C.-W. Chang, J.-Y. Wun, and M.-H. Juang, ” Quadrature injection-locked frequency dividers using dual-resonance resonator,” IEEE Microw. Wireless Compon. Lett.,. vol. 21, no. 1, pp. 37-39, Jan. 2011.
[42]S.-L. Jang, L.-T. Chou, J.-F. Huang, C.-W. Chang, ” A dual-band dual-resonance quadrature injection-locked frequency divider,” IEICE Trans. on Electron., vol. E94-C, no. 8, pp. 1336-1339, Aug. 2011.
[43]S.-L. Jang, Y.-K. Wu, C.-W. Chang, J.-F. Huang, and C.-C. Liu, ” A 90nm CMOS dual-band divide-by-2 and -4 injection-locked frequency divider,” Microwave and Optical Tech. Lett., vol. 52, no. 6, pp. 1421-1425, June 2010.
[44]S.-L. Jang, C.-C. Shih, C.-C. Liu, and M.-H. Juang, ” CMOS injection-locked frequency divider with two series-LC resonators,” Microwave and Optical Tech. Lett., vol. 53, no. 2, pp. 290-293, Feb. 2011.
[45]C.-W. Chang, S.-L. Jang, C.-W. Huang, and C.-C. Shih, " Dual-resonance LC-tank frequency divider implemented with switched varactor bias,” IEEE Int. VLSI- DAT, 2011. pp.1 – 4.
[46]S.-L. Jang, Y.-K. Wu, C.-C. Liu and J.-F. Huang, ” A Dual-band CMOS voltage-controlled oscillator implemented with dual-resonance LC tank,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 12, pp. 816-818, Dec. 2009.
[47]T. Ohira, ” Extended Adler's injection locked Q factor formula for general one- and two-port active device oscillators,” IEICE Electronics Express, vol. 7, no. 19, pp. 1486–1492. 2010.
[48]A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, “A 900 MHz CMOS LC-oscillator with quadrature outputs,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1996, pp. 392–393.
[49]J. Tang, P. Ven, D. Kasperkovitz, and A. Roermund, “Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator,” IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 657-661, May 2002.
[50]J.-H. Chang and C.-K. Kim, “A symmetrical 6-GHz fully integrated cascode coupling CMOS LC quadrature VCO,” IEEE Microw. Wireless Compon. Lett., vol. 15, no. 10, pp. 670-672, Oct. 2005.
[51]S.-L. Jang, T.-S. Lee, C.-W. Hsue and C.-W. Chang, ” A low voltage and low power bottom-series coupled quadrature VCO,” IEEE Microw. Wireless Compon. Lett., vol. 19, No. 11, 722-724, Nov., 2009.
[52]S. L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, and V. Boccuzzi, “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1148–1154, July 2003.
[53]S.-L. Jang, S.-H. Huang, C.-C. Liu and M.-H. Juang, ” CMOS Colpitts quadrature VCO using the body injection-locked coupling technique,” IEEE Microw. Wireless Compon. Lett., pp. 230-232, April, 2009.
[54]S.-L. Jang, Y.-J. Song, and C.-C. Liu, ” A differential Clapp VCO in 0.13μm CMOS Technology,” IEEE Microw. Wireless Compon. Lett., pp. 404-406, June, 2009.
[55]Y. C. Chiang, T. F. Han and H. H. Hsu, “Design of a CMOS quadrature VCO with current reuse method”, Microw. and Opti. Tech. Letts., Vol. 44, No.2, pp.202-204, Feb. 2005.
[56]T.-H. Huang and Y.-R. Tseng, “A 1 V 2.2 mW 7 GHz CMOS quadrature VCO using current-reused and cross-coupled transformer-feedback technology,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 10, pp. 698-700, Oct. 2008.
[57]Baek, D., T. Song, E. Yoon, and S. Hong, “8 GHz CMOS quadrature VCO using transformer-based tank," IEEE Microwave Wireless Components Letters, Vol. 13, No. 10, 446{448, Oct.2003.
[58]C.-Y. Yang, C.-H. Chang,and J.-H. Weng, “A quadrature CMOS VCO using a distributed MIM poly-phase network,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 2, pp. 107–109, Feb. 2011.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊
 
系統版面圖檔 系統版面圖檔