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研究生:李紫琳
研究生(外文):Tsu-lin Li
論文名稱:使用不規則性和資料反轉技術提升 NROM 為基礎的唯讀記憶體的良率
論文名稱(外文):Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs
指導教授:呂學坤
指導教授(外文):Shyue-Kung Lu
口試委員:呂學坤
口試日期:2012-12-18
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電機工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:77
中文關鍵詞:NROM良率
外文關鍵詞:NROMyield
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NROM是一種新興的非揮發性記憶體技術,具有高資料儲存能力、低製造成本以及較好的值穩定性。它也有望取代以浮動閘 (Floating gate) 為基礎的非揮發性記憶體,例如快閃記憶體 (Flash memory)。為了提升製程的良率以及改善可靠度,因此在這篇論文中提出了一種新的測試和修復流程。製程上發生的錯誤,當顧客所提供的資料寫入後,考量到在邏輯上顯現的效應,提出了錯誤遮蔽 (Fault masking) 技術以取代傳統的錯誤取代 (Fault replacement) 技術。兩種具有高遮蔽可能性的錯誤遮蔽技術被提出,分別是位址不規則性 (Address scrambling) 以及資料反轉 (data inversion),同時針對此遮蔽技術的圖學模型也被提出。另外所提出的方法也很容易整合於現有的內建自我測試電路中。我們開發故障模擬器以進行修復率 (Repair rate) 的分析,根據實驗結果顯示,修復率與製程良率均可以被大幅度的提升,除此之外硬體額外的負擔也幾乎可以被忽略。
NROM is one of the emerging non-volatile-memory technologies, which provides very high data density, low fabrication cost, and better value stability. It is also promising for replacing current floating-gate-based non-volatile memory such as flash memory. In order to raise the fabrication yield and enhance its reliability, a novel test and repair flow is proposed in this paper. Instead of the traditional fault replacement techniques, fault masking techniques are also exploited by considering the logical effects of physical defects when the customer’s code is to be programmed. Two techniques are exploited to maximize the possibilities of fault masking─address scrambling and data inversion. A control word should be incorporated into the NROM array for controlling of scrambling (including row and column scrambling). Alternatively, an extra control column is added for the data inversion technique. Graph models are also proposed for modeling the address scrambling methods. The proposed methods can be easily incorporated into the ROM BIST architectures. According to experimental results, the fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.
Abstract (in Chinese) i
Abstract ii
Acknowledgement (in Chinese) iii
Contents iv
List of Tables vi
List of Figures viii
1 Introduction 1
1.1 Motivation and Background 1
1.2 Organization 4
2 Preliminaries of One-Time-Programming Applications of NROM 5
2.1 Preliminaries of NROM Operations 5
2.1.1 Architecture of a NROM Cell 5
2.1.2 Operations of a Basic NROM Cell 7
2.1.2.1 Read Operation 7
2.1.2.2 Program Operation 9
2.2 Defect and VT Distributions of NROM-Based ROMs 10
2.2.1 Defect Distributions 10
2.2.2 Vt Distribution 12
2.3 Conventional Test and Repair Flow for NROM-Based ROMs 14
2.3.1 Conventional Redundancy Mechanism 14
2.3.2 Test and Repair Flow 15
3 A Novel Test and Repair Flow for NROM-Based ROMs 20
3.1 The Proposed Test and Repair Flow 20
3.2 Address Scrambling Techniques 24
3.2.1 Row Scrambling Technique 25
3.2.2 Column Scrambling Techniques 25
3.2.3 Problem Modeling 26
3.3 Data Inversion Technique 30
3.4 Built-In Self-Test Architectures for NROM-Based ROMs 32
3.4.1 BIST Architecture for the Row Scrambling Technique 33
3.4.2 BIST Architecture for the Column Scrambling Technique 35
3.4.3 BIST Architecture for the Data Inversion Technique 36
4 Mathematical Models for Estimating Repair Rates 38
4.1 Definitions and Notations 38
4.2 Derivation of Successful-Repair Probability 39
5 Implementation and Experimental Results 52
5.1 A Simulator for Evaluating Repair Rates 52
5.2 Graphic User Interface of the Simulator 54
5.3 Analysis of Hardware Overhead and Repair Rate 56
5.3.1 Hardware Overhead 56
5.3.2 Repair rate 65
6 Conclusions and Future Works 76
6.1 Conclusions 76
6.2 Future Works 76
References 77
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