本論文的主題在於利用硬體仿擬錯誤對動量估測架構的影響，由於VLSI 製程快速演進，使得元件尺寸縮小，造成製造時發生瑕疵的機率上昇，使良率降低，因此如何提升電路的容誤能力 (Error Tolerability) 常是被用來增加晶片有效良率之方法，錯誤 (Fault) 可被區分為不可接受錯誤 (Unacceptable Fault) 以及可接受錯誤 (Acceptable Fault)，如何快速的對錯誤進行分類成為一個需要解決的問題，我們使用現場可程式化閘陣列 (Field Programmable Gate Array) 來實現動量估測架構，在 H.264/AVC 中，動量估測模組約佔 70 % 的運算量，重要性相當高，這也是我們將此模組當作分析目標的原因。在硬體仿擬過程中，我們使用新型的錯誤注入技術將錯誤注入至處理單元陣列 (Processing Element Array) 中，不僅能降低硬體負擔 (Hardware Overhead)，也能加快仿擬的速度。另外我們會去評估錯誤發生時對於整體畫面PSNR的衰減程度，進而分析錯誤對動態向量 (Motion Vector) 的影響。最後在實驗結果中我們可以看到，利用硬體可以讓仿擬過程在毫秒間完成，而且只增加了 3 % 的硬體負擔。

Due to the rapid evolution of VLSI process technologies, the component size is gradually reduced. Therefore, the probabilities of defects occurred during the manufacturing process increase significantly and the yield losses will also increase. Improving the error tolerability of a circuit is considered a promising solution for increasing the effective fabrication yield of the chips. In this thesis, a hardware-based emulation technique is proposed to evaluate the impact of faults for motion estimation architectures. The possible faults of a circuit can be categorized into unacceptable faults or acceptable faults. How to classify the faults with negligible emulation time is a problem that should be dealt with. We use FPGAs (Field Programmable Gate Arrays) to realize the motion estimation architecture. In the H.264/AVC, the motion estimation module is very important since its computational complexity accounts for 70% of the total operations. In the implemented fault emulator, we use a new type of FIE (fault injection element) to inject faults into the processing element array. The proposed FIE can reduce the hardware overhead and speed up the emulation time. In addition, we evaluate the PSNR distortion when the faults occurred in the motion estimation module and then the error tolerability of the circuit can be analyzed. Experimental results show that the emulation can be completed in milliseconds and the hardware overhead is only about 3%.

第一章 緒論
1.1 研究動機與背景
1.2 論文綱要
第二章 視訊編碼標準與架構
2.1 視訊編碼標準
2.1.1 ITU-T標準
2.1.2 MPEG標準
2.2 視頻編碼基礎
2.3 視訊動量估測與動態補償
2.3.1 動量估測
2.3.2 動態補償
2.4 動量估測硬體設計
2.4.1 相互級平行架構
2.4.2 內部級平行架構
第三章 利用硬體仿擬之錯誤容忍技術
3.1 錯誤仿擬
3.1.1 注入固定錯誤
3.1.2 注入瞬時錯誤
3.1.3 注入反向錯誤
3.2 錯誤仿擬架構
第四章 利用硬體仿擬動量估測之錯誤容忍技術
4.1 錯誤影響分析
4.2 可接受性評估
4.3 硬體仿擬
第五章 硬體仿擬動量估測架構實現
5.1 NIOS II SOPC整合系統
5.1.1 發展板使用
5.1.2 軟體使用
5.2 動量估測電路架構
第六章 實驗數據
6.1 錯誤影響
6.2 PSNR 失真
6.3 硬體成本分析
第七章 結論
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