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研究生:陳柏瑋
研究生(外文):Po-Wei Chen
論文名稱:短距離電感耦合式無線傳輸收發機 含無參考時脈之全數位時脈資料回復電路
論文名稱(外文):Short Range Wireless and Inductive Coupling Transceiver With Reference-less All Digital Clock and Data Recovery Circuit
指導教授:姚嘉瑜
指導教授(外文):Chia-Yu Yao
口試委員:姚嘉瑜
口試日期:2012-07-24
學位類別:碩士
校院名稱:國立臺灣科技大學
系所名稱:電機工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:110
中文關鍵詞:短距離無綫通訊電感式無線傳輸收發機無參考時脈之全數位資料和時脈回復電路
外文關鍵詞:Short Range Wireless CommunicationInductive CouplingAll Digital Clock and Data Recovery Circuit (ADC
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隨著個人行動裝置漸漸被廣泛應用,短距離無綫通訊技術近年來蓬勃發展。由於行動設備透過電池供電,嚴苛限制其通訊系統在操作上,必需低功率消耗,但同時又要求高速傳輸,以應付資料量日漸龐大的多媒體檔案。電感式無線傳輸,是利用近距離磁耦合的原理傳遞脈衝信號,提供資料高速傳輸且低功率消耗的特點,無使用載波,設計難度比採用天線方式來的容易,同時也避開使用頻帶上的問題。重要的是,因為資料傳輸採用點對點的近距離(cm-range)通訊方式,在資料安全問題上風險性可較低。為了確保資料傳輸的正確率,接收端電路包括內部的放大器,需要謹慎設計以克服雜訊,但隨著傳輸速率越快,面臨的干擾、抖動問題越加嚴重,導致資料誤碼率上升,使傳輸速率面臨瓶頸。
本篇研究主題,以電感的磁耦合方式來實現高速率無線傳輸收發機,將探討傳輸時所面臨的抖動干擾,並整合無參考時脈之全數位資料和時脈回復電路(CDR),可操作在25Mbps~ 200M bps的連續速率,使接收機收到資料的同時,能獲得其時脈,且還原出較乾淨的資料訊號,以供之後做數位資料處理。透過CDR電路以增加接收機整體傳輸的正確率,可使資料傳輸有機會採用更高的速率,並降低接收端之放大器的設計難度。
本篇論文總共分為五章。其中第一章和第五章分別為導論及結論。在第二章中,將會介紹利用線圈做近距離磁耦合的原理與分析。而第三章中,將會介紹時脈資料回復電路之種類與架構,以及各個所屬之基本電路。在第四章中,實現了一個電感式無線傳輸收發機,含無參考時脈之資料和時脈回復電路,本章除了介紹晶片各區塊電路外,也著重於分析電感的設計與探討高速傳輸時的瓶頸。整顆晶片採用0.18um CMOS製程,晶片不含PAD的主體面積占0.72x0.72mm2,此系統工作在200Mbps的情況下,晶片功率消耗共56毫瓦。
In recent years, the personal mobile devices are widely used, short distance wireless communication technology grows very vigorously. Since multimedia data tends to have the large file size, high speed communication is needed to transfer the data. Also, low energy consumption is highly required because personal mobile devices are battery-powered.An wireless inductive coupling transceiver, witch transmit pulse-based signal through the short range inductive coupling, can support high-speed and lower power consumption communication feature. It has not used the signal carrier, so the work effort is easier than conventional antenna design , and can also avoid using frequency band problem. More important is the risk of data can be lower cause by the point to point cm-range transmission feature.To ensure the data be transmitted correctly, Receiver’s amplifier needs to design cautiously to avoid noise problem, but the noise and jitter problem will get worse when the transmission rate become faster, the higher bit-error rate limits the speed of data transmission.
In this work, a high speed wireless transceiver are completed by inductive coupling, and the data jitter in transmission will be discussed. Since the receiver combined with the reference-less All Digital Clock and Data Recovery Circuit(CDR), witch can be operated at 25Mbps~200Mbps continuous speed in this design, when receiver get the data, the systems have retime clock and retime data, can offer clock and low jitter data signal to DSP circuit. Through the CDR circuit to improve data accuracy, transmission will be able to use higher data rate. Meantime, the RX amplifier can be designed more easier than before.
This thesis is divided into five chapters. The chapter 1 and the chapter 5 are the introduction and the conclusion, respectively. In chapter 2, the theory and analysis of using coils to do inductive coupling in short range are described. In chapter3, introduce the various architectures of clock and data recovery circuit, including related circuit. In chapter 4, described a wireless inductive coupling transceiver with reference-less clock and data recovery circuit, include introducing all block circuit in the chip, analysis the inductor’s design and the limit of high speed transmission. The Chip is implemented by 0.18um CMOS process, Chip size is 0.72X0.72 mm2 (no included Pad size), total power dissipation is 56mW when the system working at 200Mbps.
第一章 簡介 1
1.1 前言 1
1.2 相關研究發展 1
1.3 研究動機 3
1.4 論文大綱 5
第二章 電感耦合 7
2.1 線圈自感與磁場產生 8
2.1.1 基本電磁理論及物理本質 8
2.1.2 線圈感值 10
2.2 兩線圈互感耦合效應 10
2.2.1互感與電磁感應 10
2.2.2耦合因數 12
2.2.3非理想因數 13
2.3 線圈的參數設計與模擬 13
2.3.1線圈自震頻率 13
2.3.2線圈設計 14
2.3.3線圈模擬 15
2.3.3.1 不同半徑 15
2.3.3.2 不同圈數 17
2.3.3.3 不同線寬 18
2.3.3.4 不同線距 19
2.3.3.5 距離的影響 20
2.4 實際應用與元件考量 21
第三章 時脈與資料回復電路 25
3.1 相關參數及資料取樣之原理簡介 26
3.1.1 資料形式 26
3.1.2 時間邊界(Timing Margin) 27
3.1.3 影響誤碼率的抖動參數 28
3.2 基本時脈與資料回復電路 29
3.2.1 傳統基本時脈與資料回復電路架構 29
3.2.2 線性迴路分析 31
3.2.3 數位基本時脈與資料回復電路架構 33
3.2.4 數位迴路分析 34
3.2.4.1 正比-積分形式數位迴路濾波器 35
3.2.4.2 離散數學模型分析 36
3.3 基本電路元件 44
3.3.1 頻率偵測器 44
3.3.1.1 類比Quadri-correlator頻率偵測器 44
3.3.1.2 數位Quadri-correlator頻率偵測器 47
3.3.2 相位偵測器 51
3.3.2.1 線性相位偵測器 51
3.3.2.1.1 取樣與保持相位偵測器 51
3.3.2.1.2 Hogge相位偵測器 52
3.3.2.2 非線性相位偵測器 55
3.3.2.2.1 Bang-Bang相位偵測器 56
3.3.2.2.2 Alexander相位偵測器 56
第四章 短距離電感式無線傳輸收發機含全數位資料和時脈回復電路 58
4.1 研究背景 58
4.2 研究原理與目標 59
4.3 系統架構與電路介紹 61
4.3.1 發送機 62
4.3.2 接收機 63
4.3.3 無參考時脈式全數位時脈資料回復電路 64
4.3.3.1 Alexander相位偵測器 66
4.3.3.2 頻率偵測器 67
4.3.3.3 鎖定檢測電路 68
4.3.3.4 數位控制振盪器 69
4.3.3.5 正交時脈除頻器 71
4.4 系統規格與電路模擬 72
4.4.1 傳輸線圈與電路系統之規格 72
4.4.2 接收機之電路模擬 73
4.4.3 收發機之電路模擬 76
4.4.4 數位控制震盪器之電路模擬 76
4.4.5 系統鎖定之抖動模擬 82
4.5 量測結果 86
4.5.1 晶片與量測平台 86
4.5.2 接收機前端電路之遲滯轉換量測 88
4.5.3 不同傳輸速率的抖動量測 89
4.5.4 不同傳輸距離的誤碼率量測 93
4.6 結論 101
第五章 結論與未來研究 103
5.1 論文結論 103
5.2 未來研究 105
參考文獻 107
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