跳到主要內容

臺灣博碩士論文加值系統

(18.97.14.81) 您好!臺灣時間:2025/02/11 00:41
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:陳志昇
研究生(外文):Chen, Chih-Sheng
論文名稱:改良門檻電壓的低功率全擺幅14T全加法器
論文名稱(外文):Improvement threshold loss problem of low-power full-swing 14-T full adder
指導教授:李博明
指導教授(外文):Lee, Po-Ming
學位類別:碩士
校院名稱:南台科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:101
畢業學年度:100
語文別:中文
論文頁數:89
中文關鍵詞:全擺幅全加器漣波加法器門檻電壓
外文關鍵詞:Full swingFull adderRipple adderThreshold voltage
相關次數:
  • 被引用被引用:0
  • 點閱點閱:401
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
近年來所提出的加法器電路都是以低功率、低電晶體數量為設計方向,不過大部分低電晶體數量的加法器都有門檻電壓損失(Threshold voltage loss) 問題,因此考慮低功率、低電晶體數量的設計之外,整體電路特性也是必須考慮於設計之中。

本論文提出兩種改良門檻電壓損失的低功率全擺幅 14T 全加器,利用反相器和傳輸閘電路使輸出訊號達到全擺幅狀態,並設計用於漣波進位加法器(Ripple carry adder)驗證提出電路跟文獻比較好壞。

本論文使用TSMC 0.18μm 1P6M 製程進行電路模擬以及晶片實現,以全擺幅的方向為設計要點,提出兩種14T 全加器的架構,並修改這兩種全加器加入Low-VTH 的電晶體來提高電路性能。提出的電路分別以一位元和八位元漣波加法器模擬,經由文獻比較,本論文提出的架構改良門檻電壓損失問題,使輸出訊號達到全擺幅。模擬結果顯示本論文提出的架構擁有較低的功率消耗,並實際下線製作晶片驗證提出的架構整體效能。
In recent years, proposed adder circuit at low power and low transistor counts is the design direction, but most of the low transistor count adders have a threshold voltage loss problem. Hence, consider the design of low power and low transistor counts, overall circuit performance must be considered in the design.

This paper proposes two improved threshold voltage loss of low power full swing 14-T full adder circuit. The use of inverter and transmission gate circuits so that the output signal reached full swing states. This paper designs to 8-bit ripple carry adder. To verify the proposed circuits, we compare our circuits with prior circuits.

The proposed circuits uses TSMC 0.18μm 1P6M process for simulation of the circuit and chip implementation. Base on the design key point of full swing direction, we propose two 14-T full adder structures and add Low-VTH transistors to improve circuit performance. The proposed circuits solved threshold voltage loss problem. So that the output signal reached full swing states. The simulation results shows that the proposed circuits has a lower power consumption. In addition, a chip is realized to verify overall performance of the proposed circuits.
摘要 iv
ABSTRACT v
致謝 vi
目錄 vii
圖目錄 ix
表目錄 xi
第一章 導論 1
1.1 研究背景與動機 1
1.2 研究目的 2
1.3 論文章節概要 2
第二章 背景研究 3
2.1 全加法器架構介紹 3
2.1.1 傳統全加法器架構介紹 3
2.1.2 改良型全加法器架構介紹 4
2.2 全加法器文獻介紹 6
2.2.1 SERF全加法器[2] 6
2.2.2 YUKE全加法器[7][8] 7
2.2.3 N-10T、P-10T全加法器[9] 11
2.2.4 GDI全加法器[10] 13
第三章 提出之全擺幅14T全加法器電路 15
3.1 修改的全加法器架構介紹 15
3.2 加法器電路架構分析 16
3.2.1 Module 1 (XOR-XNOR)電路 17
3.2.2 Module 2 (Sum)電路 19
3.2.3 Module 3 (Cout)電路 22
3.3 提出之全擺幅14-T全加法器 24
3.4 Low-VTH電晶體之14-T全加法器 26
第四章 模擬結果與比較 30
4.1 模擬環境介紹 30
4.2 一位元全加法器模擬結果 31
4.3 八位元漣波進位加法器模擬結果 50
第五章 晶片架構設計與量測結果 58
5.1 晶片電路架構 58
5.1.1 晶片電路架構介紹 58
5.1.2 晶片整體電路架構 61
5.1.3 晶片整體電路模擬 62
5.2 晶片佈局規劃與規格 64
5.2.1 晶片佈局與腳位規劃 64
5.2.2 晶片規格列表 67
5.3 測試考量 67
5.4 晶片實際量測結果 69
5.4.1 晶片量測方法 69
5.4.2 晶片量測結果 70
第六章 結論與未來發展 74
6.1 研究成果 74
6.2 本論文研究之優點 74
6.3 電路應用與探討 75
參考文獻 76
[1]R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, Jul. 1997.
[2]R. Shalem, E. John, and L.K John, “A novel low power energy recovery full adder cell,” Proceedings of the 1999 IEEE Great Lakes Symposium on VLSI, pp. 380–383, Feb. 1999.
[3]Nan Zhuang and Haomin Wu, “A new design of the CMOS full adder,” IEEE Journal of Solid-State Circuits, vol. 27, No.5, pp. 840-844, May 1992.
[4]V. G. Oklobdzija, M Soderstrand, and B.Duchene, “Development and Synthesis Method for Pass-Transistor Logic Family for High-Speed and Low Power CMOS,” Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems, vol. 1, pp. 298-301, 1995.
[5]Ahmed M. Shams and Magdy A. Bayoumi, “A New Full Adder Cell for low-power Applications,” Proceedings of the 1998 IEEE 8th Great Lakes Symposium on VLSI, pp. 45-49, 1998.
[6]F. Moradi, D. T. Wisland, H. Mahmoodi, S. Aunet, T. V. Cao, and A. Peiravi, “Ultra Low Power Full Adder Topologies,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3158-3161, May. 2009.
[7]H.-T. Bui, A.-K. Al-Sheraidah, and Y. Wang, “Design and analysis of 10-transistor full adders using novel XOR-XNOR gates,” in Proc. 5th Int. Conf. on Signal Processing, vol. 1, pp. 619-622, Aug. 2000.
[8]H.-T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates,” IEEE Tran. Circuits Syst. II: Analog Digit. Signal Process., pp. 25-30, Jan. 2002.
[9]F. Vasefi and Z. Abid, “10-Transistor 1-bit adders for n-bit parallel adders,” In Proceedings of the 16th International Conference on Microelectronic (ICM)s, pp. 174-177, Dec. 2004.
[10]P.-M. Lee, C.-H. Hsu, and Y.-H. Hung, “Novel 10-T full adders realized by GDI structure,” 2007 IEEE Inetrnational Symposium on Integrated Circuit (ISIC-2007), pp. 115-118, Sep. 2007.
[11]D. Radhakrishnan, “Low-voltage low-power CMOS full adder,” IEE Proc. Circuits, Devices and Systems, vol. 148, no, 1, pp. 19-24, Feb. 2001.

[12]S. Goel, A. Kumar, and M. A. Bayoumi, “Design of robust, energy-efficient full adders for deep-submicron design using hybrid-CMOS logic style,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1309-1321, Dec. 2006.
[13]D. Wang, M. Yang, W. Cheng, X. Guan, Z. Zhu, and Y. Yang, “Novel Low Power Full Adder Cells in 180nm CMOS Technology,” 2009 IEEE Industrial Electronics and Aplications(ICIEA-2009), pp. 430-433, May 2009.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top