臺灣博碩士論文加值系統

近年來，許多低功率和高速度的同步加法器電路都陸續被提出，雖然這些電路擁有低功率、高速度的特性，但是其中也有些同步加法器架構在經過多級的串接後會因為推動能力不足，導致狀態無法到達準位電壓，最終造成狀態的錯誤。本論文提出了一個雙軌非同步自我時序加法器來改良這些推動力不足的問題，其功率消耗比傳統的小，電路完成延遲時間比傳統的快。

本論文提出的雙軌非同步加法器，有漣波加法器(RCA)和前瞻進位加法器(CLA)這兩種加法器的特性。

本論文提出的電路是使用TSMC 0.18 μm 1P6M CMOS Mixed Signal RF General Purpose Standard Process FSG Al 1P6M 1.8&3.3V 製程實現，利用HSpice模擬及分析其電路特性，模擬電壓為1.5V至1.9V，輸出負載5.6ff，而實驗結果證明本論文提出的加法器電路與其他傳統電路的論文相比較後，有較低功率消耗及較快的電路運算完成時間。

Recently, many low power and high speed synchronous adders were proposed. Although these circuits possess low power and high speed characteristics, some adders suffered from insufficient driving capabilities due to a long cascade structure. Hence, the outputs of these circuits can not achieve full swing. In this paper, a dual railed self-timed adder is proposed to improve the mentioned driving problem. The power consumption is lower than the traditional circuits while speed is faster. In short, the proposed circuit can be used as a better alternative.

This paper suggests Dual rail asynchronous self-timing adder, There are other traditional adder features Ripple Carry Adder (RCA) and Carry Look-Ahead Adder (CLA) adder characteristics of these two.

The proposed circuit is realized by using TSMC 0.18 μm 1P6M CMOS Mixed Signal RF General Purpose Standard Process FSG Al 1P6M 1.8&3.3V technology. With the use of HSpice for simulation and analysis of the circuit characteristics, we simulate voltage range from 1.5V to 1.8V and output loading of 5.6ff, the paper presents experimental results prove that the adder circuit and the other papers compared to traditional circuit after, the result turns out to be lower power consumption, and faster speed Speed circuit operation time.

摘 要 iv
Abstract v
誌謝 vi
目 錄 vii
表目錄 xi
第一章 導論 1
1.1 研究背景與動機 1
1.2 研究目的 2
1.3 研究架構 3
第二章 背景研究 4
2.1 同步電路與非同步電路 4
2.1.1 同步電路 4
2.1.2 非同步電路 5
第三章 雙軌非同步自我時序加法器介紹 8
3.1 基礎元件介紹 8
3.1.1 雙軌四位元半加器 9
3.1.2 雙軌四位元INC電路 11
3.1.3 INC_REQ控制器 12
3.1.4 動態AND閘 14
3.2 四位元雙軌非同步自我時序加法器介紹 15
3.3 八位元雙軌非同步自我時序加法器介紹 17
3.4 十二位元雙軌非同步自我時序加法器介紹 18
3.5 十六位元雙軌非同步自我時序加法器介紹 21
3.6 電路平均完成延遲時間之分析 26
3.7 電路完成延遲時間機率公式推導 28
第四章 電路架構下線模擬、驗證及比較 31
4.1 電路模擬環境 31
4.2 晶片實現之電路架構 32
4.3 實現晶片之總電路模擬 36
4.4 晶片佈局規劃與規格 38
4.5 架構效能與比較 41
第五章 結論與總結 46
5.1 本論文研究之成果 46
5.2 本論文研究之優點 46
5.3 未來可能發展 47
參考文獻 48

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