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研究生:陳則翔
研究生(外文):Tse-Hsiang Chen 陳則翔
論文名稱:基於最佳EDP之動態電壓頻率調整技術與實現
論文名稱(外文):Design and Implementation of an EDP-based Dynamic Voltage and Frequency Scaling Mechanism
指導教授:梁文耀梁文耀引用關係
口試委員:賴槿峰陳彥霖
口試日期:2012-07-17
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:資訊工程系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:49
中文關鍵詞:低功耗動態電壓頻率調整記憶體存取率中央處理器使用率EDP
外文關鍵詞:Low PowerEnergy savingDVFSCPU utilizationEDP metric
相關次數:
  • 被引用被引用:0
  • 點閱點閱:222
  • 評分評分:
  • 下載下載:4
  • 收藏至我的研究室書目清單書目收藏:0
在手持式裝置的廣泛運用下,能源消耗的控管將是一個相當重要的議題,文中所採用的是眾多省電技術的其中一種「DVFS(動態頻率調節機制)」,在運行中調節至適當的頻率來達到省電的效果;往往的觀念中,只要將其頻率調至最低可達到最低能量消耗,卻忽略了調降頻率會拉長總執行時間,反而會花費這一段額外的能量消耗,而所省下的能量又小於這段額外花費的能量,才會有此一現象, 而文中採用的EDP指標正是用來權衡能量消耗與執行時間的關係;故本文中提出一個MAR-CSEDP近似方程式,透過此方程式能將我們當前的MAR值找到適當頻率,獲得最佳的EDP值[1],達到能量消耗和效能損失的降低,而這一個頻率點我們稱之為CSEDP。
在本篇論文中使用我們提出的MAR-CSEDP近似方程式,實作出EPS Governor運行在XScal PXA270上,利用MiBench這套測試程式,評估我們的演算法,最後以EDP值做為評估優劣依據,經結果顯示,我們的EPS Governor 根據MAR-CSEDP方程式較優於Ondemand Governor[2],其EDP值可下降幅度從0.429%~14.596%。


Energy saving is an important issue, especially for the handheld devices. The dynamic voltage and frequency scaling (DVFS) is one of the mechanisms in the energy saving research area. DVFS can be used to reduce energy consumption of a processor while tasks are running. However, reducing the frequency for a processor might not induce minimized energy consumption, since the execution time will be extended due to the frequency being decreased and the program will consume extra energy during this extended period. As a result, the induced extra energy could be higher than what has been saved.
Experiment results indicated that the execution time is an important factor for the energy consumption. The EDP (energy and delay product) metric[1] has been used to evaluate the trade-off between energy consumption and execution time. In this thesis, an approximation equation based on the correlation of the memory access rate and the critical speed for the minimum EDP metric is conducted for frequency and voltage prediction. The correlation equation can thus be deduced from the relationship and used at task execution time to find a frequency. According to the correlation equation, an appropriate frequency (called CSEDP) can be found to minimize the EDP.
The energy saving DVFS algorithm based on the correlation equation is presented in this thesis. The algorithm has been implemented on Linux as a kernel-space power manager. The experiment result shows that our algorithm performed better than the commonly used Linux Ondemand Governor[2]. It indicates that the EDP values are lower than that of Ondemand from 0.429% to 14.596% with 5.27% in average.


摘 要 i
ABSTRACT ii
誌謝 iv
目錄 v
表目錄 vii
圖目錄 viii
第一章 緒論 1
1.1 研究背景及動機 1
1.2 研究目標 1
1.3 論文組織與架構 2
第二章 相關文獻探討 3
2.1 動態電壓頻率調整 (Dynamic Voltage and Frequency Scaling, DVFS) 3
2.2 記憶體存取率(Memory Access Rate) 4
2.3 MAR與能量消耗 5
2.4 記憶體存取率計算公式 6
第三章 研究議題與方法 7
3.1 執行時間與能量消耗 7
3.2 EDP與MAR的相關性 11
3.2.1 EDP指標 11
3.2.2 CPU 使用率 (CPU Utilization) 15
3.2.3 EPS 演算法 15
第四章 實作方法 19
4.1 實作 19
第五章 實驗結果評估與分析 23
5.1 結果分析 23
第六章 結論 28
6.1 結論 28
6.2 未來研究方向 28
參考文獻 29
附錄A MAR-CSEDP測試程式的實驗數據及近似方程式 32
附錄B 執行在以下二十五個測試程式的實驗數據資料 41


[1] M. Horowitz, T. Indermaur and R. Gonzalez, "Low-power digital design," IEEE Symposium, Low Power Electronics, 10-12 Oct. 1994, pp.8-11.
[2]V. Pallipadi and A. Starikovskiy, "The ondemand Governor," Linux Symposium, Shared-Subtree Concept, Implementation, and Applications in Linux, 2006, pp.215-230.
[3]F. Kluge, S. Uhrig, J. Mische, B. Satzger and T. Ungerer, "Dynamic Workload Prediction for Soft Real-Time Applications," IEEE 10th International Conference on Computer and Information Technology (CIT), 2010, pp.1841-1848.
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[8]L. Yuan and G. Qu, "Analysis of energy reduction on dynamic voltage scaling-enabled systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 12, 2005, pp. 1827-1837.
[9]B. Rountree, D. K. Lowenthal, M. Schulz, and B. R. de Supinski, "Practical performance prediction under dynamic voltage frequency scaling," International Green Computing Conference and Workshops (IGCC), 2011, pp. 1-8.
[10]N. K. Jha, "Low power system scheduling and synthesis," International Conference on Computer Aided Design (ICCAD), 2001, pp. 259-263.
[11]K. Choi, R. Soma and M. Pedram, "Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times," Design, Automation and Test in Europe Conference and Exhibition, vol. 1, 2004, p. 1-4.
[12]D. Rajan, R. Zuck, and C. Poellabauer, "Workload-aware dual-speed dynamic voltage scaling," 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2006, pp. 251-256.
[13]W.-Y. Liang, S.-C. Chen, Y.-L. Chang and J.-P. Fang, "Memory-aware dynamic voltage and frequency prediction for portable devices," 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), 2008, pp. 229-236.
[14]Wireless Intel SpeedStep Power Manager. Available: http://www.intel.com/design/pca/applicationsprocessors/whitepapers/300577.htm
[15]M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge and R. B. Brown, "MiBench: A free, commercially representative embedded benchmark suite," IEEE International Workshop on Workload Characterization (WWC), 2001, pp. 3-14.
[16]M. Shalan and D. El-Sissy, "Online power management using DVFS for RTOS," The 4th International Design and Test Workshop (IDT), 2009, pp. 1-6.
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[18]NI DAQ. Available: http://www.ni.com/dataacquisition/zht/
[19]NI LabVIEW. Available: http://www.ni.com/labview/zht/


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