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研究生:邱新翔
研究生(外文):Shin-Shiang Chu
論文名稱:以平行架構之實驗設計法應用於平面規劃
論文名稱(外文):Applying Orthogonal Experiment Design to Floorplanning Using Parallel Architecture
指導教授:方志鵬方志鵬引用關係張陽朗
口試委員:宋國明陳泰蓁
口試日期:2012-07-03
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電機工程系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:35
中文關鍵詞:平面規劃正交實驗設計法模擬退火法序列對快速最長共同子序列平行運算CUDA
外文關鍵詞:FloorplanningOrthogonal Experiment DesignSimulated AnnealingSequence pairFLCSCUDA.
相關次數:
  • 被引用被引用:1
  • 點閱點閱:118
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
傳統積體電路設計流程中,平面規劃是很重要的一環,隨著晶片內模組的增加,計算複雜度也大幅提升,所以需要對傳統的演算法作些改變。我們推出正交表,表中的各因子代表模組,任一因子的準位代表該模組之方向。以此正交表可以明顯縮小解空間。
我們選擇使用序列對(Sequence Pair)表示法來表示電路平面,並且搭配快速最長共同子序列(Fast Longest Common Subsequence)來計算面積,最後整合模擬退火演算法和直交表,藉由解空間的縮小而加快得出較佳解的速度。
由於正交實驗設計法需要大量的運算,所花費時間較長,我們使用CUDA架構的平行運算,來解決這個問題。


Floorplanning is an important and dispensable stage in the traditional integrated circuit design process. With the raised module numbers and increased wire length, the computation complexity is raised dramatically. Obviously, the traditional algorithms need to be updated. We developed an orthogonal table, in which each factor represents a module and the level of a specified factor denotes the orientation of that module. With this orthogonal table, the solution space is significantly decreased.
We use sequence pair to represent a floorplan and the fast longest common subsequence is used accordingly to calculate the area of a floorplan. Different floorplans are generated by perturbation in a simulated annealing process. During simulated annealing, we integrate orthogonal table to scale down the solution space and thus promote the speed of obtaining better solution.
Although the solution space is reduced by orthogonal table, the computation time for deriving the area of each solution is inevitably increased. We use CUDA-based parallel technology to solve this problem.

摘 要 I
Abstract II
誌 謝 III
目 錄 IV
表目錄 VI
圖目錄 VII
第一章 緒論 1
1.1研究背景 1
1.2研究動機 2
1.3論文架構 2
第二章 相關文獻 3
2.1序列對表示法 3
2.2快速最長相同子序列 5
2.3模擬退火(Simulated Annealing)法 8
2.4 正交實驗設計(Orthogonal Experiment)法 9
2.5 平行運算(CUDA) 12
第三章 研究方法 14
3.1概述 14
3.2初始解與大量擾動 15
3.3模擬退火階段 18
3.4正交實驗設計法應用(OED) 21
第四章 實驗結果 27
4.1實驗環境 27
4.2實驗結果 27
第五章 結論與未來展望 33
5.1 結論 33
5.2 未來展望 33
參考文獻 34


[1]NaveedSherwani, Algorithms for VLSI Physical Design Automation, 3th Ed., KAP, 1999.
[2]Sadiq M. Sait, Habib Youssef, VLSI Physical Design Automation: Theory and Practice, Word Science, 2006.
[3]D. F. Wong, and C. L. Liu, “A New Algorithm for Floorplan Design,”IEEE Proc. DAC, 1986, pp. 101-107.
[4]Nakaya S., Koide T. and Wakabayashi S., “An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair,” Proc. IEEE ISCAS, 2000, pp. 65-68.
[5]Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang., “GPE: A New Representation for VLSI Floorplan Problem,” IEEE Proc. ICCD, 2002, pp. 531-533.
[6]Y. Pang, C.K. Cheng, and T. Yoshimura, “An enhanced perturbing algorithm for floorplan design using the O-tree representation,”IEEE Proc. ISPD, 2000, pp. 168-173.
[7]Yun-Chih Chang; Yao-Wen Chang; Guang-Ming Wu; Shu-Wei Wu,“B*-trees: A New Representation for Non-slicing Floorplans,” IEEE Proc. DAC, 2000, pp. 458-463.
[8]X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C.-K. Cheng, and J. Gu,“Corner block list: an effective and efficient topological representation of non-slicing floorplan,”IEEE Proc. ICCAD, 2000, pp. 8-12.
[9]Jai-Ming Lin and Yao-Wen Chang, “TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans,”IEEE Proc. DAC, 2001, pp. 764-769.
[10]H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “VLSI Module Placement Based on Rectangle-Packing by the Sequence-Pair,” IEEE Transaction on Computer Aided Design of Integrated Circuit and System, Vol. 15, no.2, February 1996, pp. 1518-1524.
[11]X. Tang, R. Tian, D.F. Wong, "Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 20, no. 12, December 2001, pp. 1406-1413.
[12]Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin, ”IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs,” IEEE Proc. ICCAD, 2005, pp. 159-164.


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