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研究生:李振銘
研究生(外文):Chen-Ming Li
論文名稱:應用在WCDMA RF-repeater回授訊號消除模組之硬體設計與實現
論文名稱(外文):The Hardware Design and Implementation of Echo-Cancellation Module for RF-repeater in WCDMA Systems
指導教授:張正春張正春引用關係
口試委員:蔡佩芸郭天穎譚旦旭
口試日期:2012-07-24
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電機工程系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:117
中文關鍵詞:中繼器回授訊號消除FPGAVerilog HDL最小均方演算法
外文關鍵詞:RepeaterEcho-CancellationFPGAVerilog HDLLMS
相關次數:
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本研究以自適應回授訊號干擾消除技術為基礎發展高增益WCDMA系統之中繼器(Repeater),以達到除去回授(Feedback)訊號,以優化使用高增益中繼器之通訊品質。研究採取硬體描述語言HDL撰寫FPGA發展回授訊號消除模組(Echo-Cancellation Module),此發展模組包含自適應回授訊號消除器、半波濾波器(Half-band filter)、低通濾波器(Low-pass filter)、降頻器(Down sample)、升頻器(up sample)、鎖相環迴路(PLL)、以及A/D、D/A等元件,其中自適應回授訊號消除器以pipeline技術實現LMS、NCLMS、DLMS、PIPLMS等演算法。本研究結果由訊號產生器、頻譜分析儀和Altera DE2-115 FPGA平台驗證具回授訊號消除之WCDMA中繼器。所設計之模組操作增益可達Excess isolation -10dB。

In this thesis, we develop a echo-cancellation module (ECM) for high-gain in-band repeater in WCDMA systems. Baseband signal processing along with adaptive signal processing technology is utilized and implemented on FPGA boards. The designed ECM includes an adaptive feedback signal canceller, half-band filters, low-pass filters, down sample converters, up sample converters, phase lock loops (PLL), analog to digital (A/D) convernters, and digital to analog (D/A) converters. The implemented algorithms in the feedback signal canceller includes the Least Mean Squares(LMS), Non-Canonical Least Mean Squares(NCLMS), Delay Least Mean Squares(DLMS), and Pipeline Least Mean Squares(PIPLMS) algorithm.The designed ECM is examined by using signal generator, spectrum analyzers and Altera the DE2-115 FPGA platform, to demostrate a high-gain WCDMA repeater with the feedback signal cancellation functionality. The designed ECM can operate at the excess isolation up to -10dB.

摘 要 i
ABSTRACT ii
誌 謝 iii
目錄 iv
表目錄 vii
圖目錄 ix
第一章緒論 1
1.1前言 1
1.2研究動機與方法 1
1.3論文架構 3
第二章WCDMA系統與中繼器相關背景知識之介紹 4
2.1行動通訊的歷史演變 4
2.2 WCDMA的介紹 7
2.2.1 WCDMA的技術特性 7
2.2.2 功率控制 8
2.2.3 交遞(Handover) 11
2.3 中繼器介紹 13
2.3.1 中器繼之趨勢發展 14
2.3.2 中繼器常見的問題 14
第三章回授消除模組之基本原理與設計 17
3.1 管線化(Pipeline)技術原理 17
3.2 回授訊號消除架構 18
3.3自適應演算法 20
3.3.1 LMS演算法 20
3.3.2 NCLMS演算法 26
3.3.3 PIPLMS演算法 29
3.4 抽取(Decimation)器 34
3.5 內插(Interpolation)器 36
第四章FPGA基本原理與設計 38
4.1 FPGA設計原理 38
4.2 Quartus II與ModelSim 應用 39
4.2.1硬體描述語言原理介紹 41
4.2.2時序分析概念 42
4.2.2.1 建立時間與保持時間(Setup & Hold) 43
4.2.2.2 Clock約束 44
4.2.2.3 I/O約束 45
第五章 自適應回授訊號消除之模擬與實驗硬體架構結果與分析 48
5.1以Verilog HDL實現自適應演算法與各通訊元件 48
5.1.1加/減法器及乘法器之實現與模擬 48
5.1.2 抽取(Decimation)器之實現與模擬 50
5.1.3內插(Interpolation)器之實現與模擬 54
5.1.4 FIR濾波器之實現與模擬 57
5.1.5自適應濾波器控制係數更新方程式實現與模擬 59
5.1.5.1 LMS控制係數更新方程式之實現與模擬 59
5.1.5.2 NCLMS控制係數更新方程式之實現與模擬 61
5.1.5.3 PIPLMS控制係數更新方程式之實現與模擬 63
5.2硬體模擬系統架構之實現與模擬分析 66
5.2.1抽取器與內插器之實現與模擬分析 66
5.2.2 回授消除模組之實現與模擬分析 68
5.2.2.1 自適應濾波器LMS演算法之模擬分析 72
5.2.2.2自適應濾波器LMS演算法使用Pipeline技術架構一之模擬與分析 79
5.2.2.3自適應濾波器LMS演算法使用Pipeline技術架構二之模擬與分析 82
5.2.2.4自適應濾波器NCLMS演算法之模擬分析 85
5.2.2.5自適應濾波器NCLMS演算法使用Pipeline技術之模擬分析 88
5.2.2.6自適應濾波器PIPLMS演算法之模擬分析 90
5.2.2.7自適應濾波器DLMS演算法之模擬分析 94
5.2.2.8數據綜合分析 97
5.3整體規劃 99
5.4實驗儀器介紹 100
5.4.1 Altera DE2-115開發版 102
5.4.2 AD/DA模板 103
5.5硬體實測結果與分析 103
5.5.1抽取器與內插器之設計結果 105
5.5.2自適應濾波器之設計結果 109
第六章結論與未來發展 113
參考文獻 114



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