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研究生:陳世昕
研究生(外文):Shin-Hsin Chen
論文名稱:二加一階多位元切換電流式三角積分調變器設計與實作
論文名稱(外文):Design and Implementation of 2+1 Order Switched-Current Delta-Sigma Modulator with 3-bit Quantizer
指導教授:宋國明宋國明引用關係
口試委員:謝祥圓楊維斌黃育賢
口試日期:2012-07-06
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電機工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:73
中文關鍵詞:二加一階三角積分調變器切換電流式多位元量化器資料權重平均演算法
外文關鍵詞:delta-sigma modulatorswitched-current techniquemulti-bit quantizer
相關次數:
  • 被引用被引用:2
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本論文旨在研究一個應用於語音系統之三角積分調變器,該調變技術對類比電路的非理想特性並不敏感,非常適合用來實現高解析度、高精準度的類比數位轉換器。提升系統階數一直是三角積分調變器提高解析度的方法。在單一迴路(single loop)和多路徑迴路(Interpolative)的高階系統中,系統的穩定度通常是設計者的一大隱憂,因此透過低階的系統來實現多級串接(MASH),以達到相對穩定的高階架構。此外,透過多階量化器來達成高解析度,並藉由資料權重平均演算法(DWA)來改善數位類比轉換器的非線性效應,降低其對系統的影響。
在電路系統的實現上,採用TSMC 0.18 μm的互補式金氧半導體製程參數來設計與模擬。模擬結果顯示,二加一階三位元多級串接架構,在取樣頻率為5.12百萬赫(MHz)與超取樣率(OSR)為128的條件下,其有效訊號頻寬為20仟赫(kHz),且其訊號雜訊失真比可達110分貝(dB),相當於有效位元數(ENOB)約18.04位元;而晶片於1.8V的供應電壓下,其消耗功率約為21.4mW,電路的工作電流範圍為-5μA~+5μA。


A sigma-delta modulator (SDM) is proposed in this thesis for audio system.SDM is well suitable for the realization of a high-resolution,high-accuracy and narrow-band analog-to-digital converter (ADC) because this modulator is insensitive to the imperfections on analog components.The higher the order is,the higher the resolution is for SDM. There are several types of high-order SDM, such as single-loop archiecture, interpolative archiecture and multi-stage noise shaped (MASH) archiecture.The stability is serious problem for single-loop and interpolative architecture. MASH is a cascade architecture of low-order stages.That is, the whole MASH archiecture walks stable. Besides, the multi-bit quantizer to is used accomplish high resolution, and that the nonlinear error of DAC can be improved with data weighted averaging (DWA) logic.
The systematic simulation was completed with TSMC 0.18 μm CMOS process. The simulation results show that the sampling rate is 5.12 MHz, the oversampling ratio is 128, and the signal bandwidth is 20 kHz for audio system. Moreover the signal-to-noise and distortion ratio(SNDR),the effective number of bit (ENOB),and the power consumption are 110 dB,18.04 bits,and 21.4 mW,respectively,with the supply voltage of 1.8V.and with input current range of -5 μA~+5 μA.


摘 要 i
ABSTRACT ii
誌 謝 iii
目 錄 iv
表目錄 vi
圖目錄 vii
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構與章節 1
第二章 類比數位轉換器原理與架構 2
2.1 訊號處理系統 2
2.2 類比數位轉換器簡介 3
2.3 類比數位轉換器操作原理 5
2.3.1 奈奎氏取樣率類比數位轉換器 5
2.3.2 超取樣類比數位轉換器 9
2.4 三角積分類比數位轉換器 13
2.4.1 雜訊頻移技術 13
2.4.2 內插架構 18
2.4.3 多級串接架構 19
2.4.4 多位元三角積分調變器 20
2.5 效能之定義 21
第三章 系統架構與MATLAB行為模擬 23
3.1 系統設計流程 23
3.2 轉移函數及系統行為模擬 24
3.2.1 二階三位元模擬 24
3.2.2 二加一階三位元模擬 27
第四章 三角積分調變器實現 32
4.1 系統設計 32
4.2 切換電流技術 32
4.3 非理想效應 34
4.3.1 不匹配 34
4.3.2 傳輸誤差 36
4.3.3 脈衝穿透誤差 37
4.3.4 雜訊 39
4.3.5 非理想效應之補償 40
4.4 子電路設計與模擬 45
4.4.1 積分器 45
4.4.2 電流式比較器 51
4.4.3 三位元量化器 52
4.4.4 偏壓電流電路 53
4.4.5 電流式數位類比轉換器 54
4.4.6 非重疊時脈產生器 56
4.4.7 資料權重平均器 57
4.5 二加一階三位元電路系統模擬 59
第五章 電路佈局與量測 65
5.1 製程變異 65
5.2 佈局考量 65
5.3 晶片佈局 67
5.4 量測環境 68
第六章 結論與未來研究方向 70
6.1 結論 70
6.2 未來研究方向 70
參考文獻 71

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