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研究生:徐明震
研究生(外文):Ming-Cheng Hsu
論文名稱:10位元200-MS/s切換電流式管線型類比數位轉換器之設計
論文名稱(外文):Design of a 10-bit 200-MS/s Switched-Current Pipelined Analog-to-Digital Converter
指導教授:宋國明宋國明引用關係
口試委員:謝祥圓楊維斌黃育賢
口試日期:2012-07-06
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電機工程系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:102
中文關鍵詞:類比數位轉換器管線型類比數位轉換器取樣保持電路
外文關鍵詞:Switched-currentanalog-to-digital converterpipelined ADCsample and hold circuitOP feedback
相關次數:
  • 被引用被引用:4
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本論文旨在設計一種低功率十位元切換電流式管線型類比數位轉換器,其架構共計九級,前面八級為1.5位元的架構,最後一級為兩位元架構,據此完成十位元的管線型架構。此外,本論文也利用數位校正電路來校正比較器所造成的誤差,並在切換電流式的架構下,利用OP回授式電流鏡來降低輸入阻抗,以及虛開關來減少與輸入訊號相關的通道電流和電荷注入效應,藉此得到信號匹配的精確度及改善傳遞誤差。
本論文提出一個取樣率可達到200M-Samples/sec、解析度10位元的管線型類比數位轉換器,整體架構於第五級以後將取樣保持電路的回授OP分享共用,以減少九分之一的OP使用數量,以有效降低整體電路的消耗功率及面積。
在採用TSMC 0.18μm 1P6M標準製程下,其模擬結果顯示,在輸入頻率5MHz的弦波訊號及取樣率為200MHz的條件下進行模擬,其最大的訊號雜訊失真比(SNDR)可達到56.5dB,相當於解析度約9.09位元;晶片在1.8V的供應電壓下,消耗功率約為48.9mW,電路的工作電流範圍為-20μA~+20μA,FOM值可達0.47pJ/conversion,微分非線性誤差(Differential Nonlinearity, DNL)為0.7LSB,積分非線性誤差(Integral Nonlinearity, INL)為0.7LSB。核心晶片面積約為1.000×0.631 mm2。


The thesis presents a low power switched-current analog-to-digital converter(ADC) which consists of 8 stages in 1.5-bit/stage, and one stage in 2-bit/stage.Notify that a digital error correction circuit is used to correct the offset error of comparator in pipelined ADC. Furthermore, not only the OP feedback is used to decrease the input impedence, but also the dummy switch is adopted to decrease the signal-dependent channel current and the charge-injection error. Those adopted techniques can decrease the transmission error considerately.
Next, this study can save power concumption by using the amplifier-sharing technique ; and that the chip area can be reduced roughly one-ninth (1/9). The simulation According to simulation results, show that the Signal-to-Noise and Distortion Ratio(SNDR) is 56.5dB whose effective number of bit (ENOB) is 9.09bits at the input frequency of 5MHzand the sampling rate of 200Ms/s in the proposed pipelined ADC fabricated in TSMC 1P6M 0.18-μm CMOS process; and that the power consumption is 48.9mw at the supply voltage of 1.8 V. Notify that the figure of merit, differential nonlinearity(DNL),and integral nonlinearity(INL) are0.47pJ/conversion, 0.7LSB, and 0.7LSB,respectively,at the operational current range between -20μA and +20μA.


摘 要 i
Abstract iii
誌謝 v
目錄 vi
表目錄 ix
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 3
第二章 管線型類比數位轉換器架構概述 4
2.1 類比數位轉換器效能參數 4
2.1.1 動態特性參數 4
2.1.2 靜態特性參數 10
2.2 快閃式類比數位轉換器電路架構 14
2.3 兩階式類比數位轉換器電路架構 15
2.4 管線化類比數位轉換器之架構原理 16
第三章 系統設計與模擬 20
3.1 數位誤差校正與單級1.5位元的工作原理 20
3.2 電流模式之架構與演算方法 25
3.3 管線型 ADC的行為模擬 31
3.3.1 前端取樣保持電路 31
3.3.2 1.5位元子類比數位轉換器 32
3.3.3 子數位類比轉換器 32
3.3.4 單級1.5位元電路 33
3.3.5 2位元類比數位轉換器 34
3.3.6 非理想效應考量 35
3.3.7 全部系統架構模擬 37
第四章 電路設計與模擬 42
4.1 切換電流技術 42
4.2 電流鏡設計考量 53
4.3 類比電路之設計及模擬結果 59
4.3.1 取樣保持電路 59
4.3.2 低輸入阻抗電流比較器 66
4.3.3 1.5位元之子類比數位轉換器 68
4.3.4 2位元之子類比數位轉換器 70
4.3.5 數位類比轉換器電路 71
4.4 數位電路之設計及模擬結果 73
4.4.1 暫存器電路 73
4.4.2 數位錯誤更正電路 74
4.4.3 非重疊時脈產生器 76
4.5 放大器共用之ADC設計 77
4.6 整體電路結果 80
4.7 效能總結與規格比較 88
第五章 系統佈局與量測 90
5.1 電路佈局 90
5.2 量測環境 91
5.3 測試結果 93
第六章 結論與未來研究方向 98
6.1 結論 98
6.2 未來研究方向 98
參考文獻 99


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