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研究生:謝明廷
研究生(外文):Ming-Ting Hsieh
論文名稱:低面積之可調多路徑FFT處理器設計
論文名稱(外文):An Area-Efficient Adaptive Multi-path FFT Processor
指導教授:李宗演李宗演引用關係
口試委員:蔡加春熊博安
口試日期:2012-06-28
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:52
中文關鍵詞:Partial Dynamic ReconfigurationFPGAFFTMIMO-OFDM
外文關鍵詞:Partial Dynamic ReconfigurationFPGAFFTMIMO-OFDM
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  • 被引用被引用:1
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本文提出一個應用於動態可重組FPGA上之可調路徑FFT處理器,利用動態可重組技術使FFT處理器能靈活的在各種不同點數與路徑數之間做切換而不影響整體MIMO-OFDM系統之運算,讓系統能有效的在不同的通訊協定之間做轉換。該處理器可切換成4組2路徑、2組4路徑或是1組8路徑的運算模式,在運算點數部分則可分別切換成64、128或256點運算的FFT處理器,此外為了減少因MDF架構而所增加的硬體資源,文中以旋轉因子較為規律的FFT Radix-2演算法為架構基底,將路徑中所有的複數乘法器預先轉換成硬體資源較少的可重組的位移與加法電路,利用可重組FPGA精簡的配置需要的組合至電路上,達到減少硬體資源使用之目的。在實驗中平均約可省下FPGA上26.18%的Slice資源,並且在架構中無需使用儲存旋轉因子的記憶體空間。

In this work, we propose an architecture for adaptive multi-path Fast Fourier Transform (FFT) processor using Partial Dynamic Reconfiguration (PDR) FPGA devices. Reconfiguration technology provides the flexibility of switching FFT points and paths without compromising integrity of the Multiple Input Multiple Output-Orthogonal Frequency Division Multiplexing (MIMO-OFDM) system, enabling us to target different wireless protocol for conversion. The proposed architecture is easy to switch a 8- path, 4- path and 2- path FFT processor with variable-length including 256, 128, and 64 points for MIMO-OFDM systems. Furthermore, in order to reduce the hardware resources in the Multi-path Delay Feedback (MDF), we convert all the complex multipliers in FFT processor to the constant multiplier, eliminating the ROM used to store twiddle factor and the complex multiplier resources. In our experiments, not only can we save about 26.18% of the resources on the Slice, but we also eliminate the need to use any ROM on FPGA.

目 錄
中文 摘要 ................................ ................................ ................................ ........................... i
英文摘要 ................................ ................................ ................................ ......................... iii
誌謝 ................................ ................................ ................................ ................................ . iii
目錄 ................................ ................................ ................................ ................................ . iv
表目錄 ................................ ................................ ................................ ............................. vi
圖目錄 ................................ ................................ ................................ ............................ vii
第一章 緒論 ................................ ................................ ................................ .................. 1
1.1 簡介 ................................ ................................ ................................ .............. 1
1.2 研究動機與目的 ................................ ................................ .......................... 3
1.3 本論文之貢獻 ................................ ................................ .............................. 3
1.4 論文架構 ................................ ................................ ................................ ...... 4
第二章 相關文獻探討 ................................ ................................ ................................ .. 5
2.1 RADIX ADIX-2 FFT 演算法與架構介紹 演算法與架構介紹 ................................ ................................ 5
2.1.1 RadixRadixRadix -2演算法 ................................ ................................ .................... 5
2.1.2 RadixRadixRadix -2之硬體架構 之硬體架構 ................................ ................................ ............ 7
2.1.3 FFT 處理器架構 ................................ ................................ .................. 9
2.2 動態部分可重組系統 動態部分可重組系統 ................................ ................................ ................ 11
第三章 系統架構與模型 ................................ ................................ ............................ 12
3.1 多路徑 FFT 處理器模型 處理器模型 ................................ ................................ ............ 12
3.2 FFT 路徑與運算基底 路徑與運算基底 ................................ ................................ ................. 14
3.3 旋轉因子乘法器之設計 旋轉因子乘法器之設計 ................................ ................................ ............ 15
3.3.1 旋轉因子計算 ................................ ................................ .................... 15
3.3.2 可重組位移乘法器架構 ................................ ................................ .... 17
第四章 可調多路徑 FFTFFTFFT處理器之設計 ................................ ................................ .... 18
4.1 多路徑 FFT 處理器硬體架構 處理器硬體架構 ................................ ................................ .... 18
4.2 重組控制器架構 ................................ ................................ ........................ 21
4.2.1 ICAP Processor................................ ................................ .................. 23
4.2.2 切換處理流程 ................................ ................................ .................... 24
4.3 可重組區域電路 ................................ ................................ ........................ 25
4.3.1 Reconfigurable Area 1................................ ................................ ........... 25
4.3.2 Reconfigurable Area 2................................ ................................ ........... 26
第五章 實驗結果 ................................ ................................ ................................ .......... 27
5.1 系統平台與設定 ................................ ................................ .......................... 27
5.2 多路徑 FFT 處理器之實作結果 處理器之實作結果 ................................ ................................ . 27
5.2.1 靜態資源分析 ................................ ................................ ...................... 27
5.2.2 動態資源使用分析 ................................ ................................ .............. 30
5.3 效能比較 ................................ ................................ ................................ ...... 34
第六章 結論與未來工作 ................................ ................................ .............................. 37
6.1 結論 ................................ ................................ ................................ .............. 37
v
6.2 未來工作 ................................ ................................ ................................ ...... 37
參考文獻 ................................ ................................ ................................ ........................ 38
附錄:已刊登或接受之論文 ................................ ................................ ........................ 40


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