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研究生:沈瑋傑
研究生(外文):Wei-Chieh Shen
論文名稱:低延遲同步輸出平行渦輪解碼器晶片設計
論文名稱(外文):Chip Design of Low Latency Parallel Turbo Decoder with Synchronous Output
指導教授:李文達李文達引用關係
指導教授(外文):Wen-Ta Lee
口試委員:黃育賢劉遠楨
口試委員(外文):Yuh-Shyan HwangYuan-Chen Liu
口試日期:2012-06-20
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:67
中文關鍵詞:渦輪解碼器平行架構無衝突低延遲
外文關鍵詞:Turbo decoderparallel architectureContention-freelow latency
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渦輪碼具有絕佳的解碼效能,是最接近Shannon-limit的錯誤更正碼之一。為了符合現代通訊的需求,渦輪碼在直覺上使用多個SISO解碼器平行解碼以加快速度。然而,平行解碼器方式,往往因為縮短交錯器的長度而明顯降低錯誤更正效能。因此本論文提出一個低延遲同步輸出平行渦輪解碼器來同時改善延遲與錯誤更正能力,在作法上使用無衝突設計之交錯器來達成與傳統渦輪解碼器相似的效果,再讓兩個SISO解碼器同時解碼、輸出資料,進而提高資料吞吐量。模擬結果顯示錯誤更正能力非常接近於傳統的渦輪解碼器,而在不同碼寬長度的情況下,也可以減少51.3%~58.6%的延遲時間,此解碼器可以在100MHz 的工作頻率進行八次疊代下,可提供11.7Mbps的資料吞吐量。我們將所提出的低延遲同步輸出平行渦輪解碼器在Xilinx Virtex-5 FPGA平台上驗證功能性;另外我們也採用TSMC 0.18μm 1P6M COMS製程來完成整體晶片合成與佈局,解碼晶片邏輯閘數量為151396,大小為3.42mm2。

Turbo code has excellent decoding performance which is one of close to the Shannon-limit error correction codes. In order to achieve requirement of the modern communication, turbo codes employ multiple SISO decoders by intuition. However, parallel decoders will degrade the correcting performance dramatically as a result of shortening the interleaver length. Thus in this thesis, we proposed a low latency parallel decoding with synchronous output turbo decoder. It can improve both latency and error correction ability in comparison with general parallel turbo decoders. Simulation results show that the error correction ability is close to the traditional turbo decoder and the whole decoding latency can be reduced 51.3%~58.6% with different block length, also can achieve 11.7Mbps throughput with 8 iterations at 100MHz working frequency. For verifying this work, we have used FPGA to emulate the hardware architecture and designed this chip with TSMC 0.18μm CMOS process. The gate count is 151396. The chip size including I/O pad is 3.42mm2.

Contents

Chinese Abstract i
English Abstract ii
Acknowledgement iii
Contents iv
List of Tables vii
List of Figures viii
CHAP. 1 Introduction 1
1.1 Background and Motivation 1
1.2 Thesis Objectives 3
1.3 Organization of the Dissertation 3
CHAP. 2 Turbo Code 4
2.1 Turbo Encoder 5
2.2 Interleavers 6
2.2.1 Block Interleaver 6
2.2.2 Random Interleaver 7
2.2.3 S-Random Interleaver 7
2.3 Iterative Decoding Process 8
2.3.1 MAP Algorithm 9
2.3.2 Max-Log-MAP Algorithm 14
2.3.3 Log-MAP Algorithm 16
CHAP. 3 Design and Architecture of Low Latency Parallel
Turbo Decoder with Synchronous Output 18
3.1 Traditional Low Latency Turbo Decoder Technique 18
3.1.1 Traditional Sliding Window Technique 19
3.1.2 Parallel Phase Decoding Turbo Decoder Technique 20
3.2 Low Latency Parallel Turbo Decoder with
Synchronous Output Technique 22
3.2.1 Contention-free Interleaver 22
3.2.2 The Sliding Window of Proposed Technique 25
3.2.3 The Dependence of Overlapping Data 27
3.2.4 The Simulation of Proposed Technique 31
3.3 ASIC Architecture of Low Latency Parallel Turbo Decoder with Synchronous Output 33
3.3.1 Received Data Buffers 34
3.3.2 Interleaver Buffer 35
3.3.3 Extrinsic Data Buffers 36
3.3.4 VLSI Architecture of the SISO Decoder 38
3.3.4.1 Branch Metric Calculation Unit (BMC) 39
3.3.4.2 State Metric Calculation Unit (Alpha, Beta, Beta Initial) 39
3.3.4.2.1 Add-Compare-Select with Offset Circuit (ACSO) 40
3.3.4.2.2 Normalization Circuit 41
3.3.4.3 State Metric Memory (SMM) 42
3.3.4.4 Log-Likelihood Ratio Calculation Unit (LLR) 42
3.3.4.5 Extrinsic information Calculation Unit (Le) 43
CHAP. 4 Verifications of Low Latency Parallel Turbo Decoder with
Synchronous Output 44
4.1 System Specifications 44
4.2 RTL Design and Simulations 46
4.3 Emulations of the FPGA Board 48
4.3.1 FPGA Design Flow 48
4.3.2 Emulations of Function 49
4.4 Chip Synthesis and Layout 52
4.4.1 Cell-based IC Design Flow 52
4.4.2 Chip Layout 53
4.5 Performance and Comparison 55
CHAP. 5 Conclusion and Future Work 57
5.1 Conclusion 57
5.2 Future Work 58
References 59
Appendix: Accepted Paper 63



References

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