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研究生:張隆盛
研究生(外文):Lung-Sheng Chang
論文名稱:低功率類比式低密度同位元校驗碼解碼器晶片設計
論文名稱(外文):IC Design of Low-power Analog LDPC Decoder
指導教授:李文達李文達引用關係
口試委員:黃育賢劉遠楨
口試日期:2012-06-20
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:69
中文關鍵詞:類比式解碼器低密度同位元校驗碼最小和演算法電流模式電路吉爾伯特乘法
外文關鍵詞:Analog DecoderLDPCMin-sum algorithmCurrent ModeGilbert Multiplier
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  • 被引用被引用:4
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本論文提出一新型低功率類比式低密度同位元校驗碼解碼器晶片設計。此電路架構是以低密度同位元校驗碼為設計基礎,其常見演算法為和積演算法及最小和演算法,而最小和演算法是經由和積演算法化簡而來,由公式推導過程中得知,乘法器具有取最小值的特性,所以本論文採用最小和演算法設計電路為主,並以乘法器作為校驗電路之基礎,不僅有助於提升電路解碼速度,且整體電路以電流模式電路實現,可有效化簡電路複雜度,進一步降低了整體電路的功率消耗以及晶片面積,達成低功率和低成本之訴求。
最後我們以TSMC 0.18μm 1P6M CMOS 製程技術設計驗證,此晶片包含14996顆電晶體,其工作電壓為1.8V,解碼速度為32-Mb/s,功率消耗為4.26mW,功率速度比為0.13nJ/b,整體晶片面積為1.198*1.123mm2,不含I/O PAD面積為0.805*0.685mm2。


This thesis proposed a new low-power analog low-density parity check (LDPC) code decoder chip design. This circuit architecture based on low-density parity check codes. The common algorithm has the sum-product algorithm and the min-sum algorithm. The latter is simplified from the sum-product algorithm. On the handling formula process, we can find the multiplier characteristic with taking the minimum, so the min-sum algorithm is used in the circuit design. Besides, the multiplier can also increase the circuit decoding speed. Finally, the whole circuit is implemented by current-mode. It will effectively reduce the circuit complexity, further reduce the overall circuit power consumption and chip area, and reached the demands of the low power and low cost.
The proposed analog LDPC decoder is implemented by using TSMC 0.18μm 1P6M CMOS technology. 14996 transistors are used in this chip. When the throughput and supply voltage is 32 Mb/s and 1.8V respectively, the power consumption is only 4.26 mW. The power/speed ratio is 0.13nJ/b. The chip size is 1.198*1.123 mm2, and not including I/O PAD size is 0.805*0.685mm2.


中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 緒論 1
1.1 研究動機 1
1.2 相關研究探討 2
1.3 論文組織介紹 3
第二章 低密度同位元校驗碼 4
2.1 線性區塊碼 4
2.2 低密度同位元校驗碼基本概念 6
2.2.1 低密度同位元校驗碼矩陣 7
2.2.2 Tanner Graph 7
2.2.3 Cycle與Girth效應 8
2.3 低密度同位元校驗碼編碼程序 9
2.4 低密度同位元校驗碼解碼程序 10
2.5 低密度同位元校驗碼演算法 11
2.5.1 和積演算法 11
2.5.2 最小和演算法 14
第三章 類比式(32,8)低密度同位元校驗碼之解碼器設計 16
3.1 類比式(32,8)LDPC解碼器電路設計原理 17
3.2 類比式(32,8)LDPC解碼器整體架構 20
3.2.1 位元節點電路實現 21
3.2.2 校驗節點電路實現 24
3.2.2.1 實數值對絕對值及符號轉換電路 25
3.2.2.2 吉爾伯特乘法器 27
3.2.2.3 差動疊接式電壓開關邏輯互斥或閘電路 32
3.2.2.4 絕對值及符號對實數值轉換電路 33
3.2.3 五位元正負號電流式數位-類比轉換電路 35
3.2.4 輸入輸出介面 37
3.2.4.1 暫存器與五對三十二解碼器 37
3.2.4.2 三十二對一多工器 38
3.3 類比式(32,8)LDPC解碼器整體電路模擬 39
3.4 類比式(32,8)LDPC解碼器之WER分析 44
第四章 整體電路之佈局與量測結果 45
4.1 類比式(8,4)LDPC解碼器電路佈局與晶片量測 46
4.2 類比式(32,8)LDPC解碼器電路佈局與晶片量測 53
第五章 結論與未來展望 60
參考文獻 61
附錄A
待投稿論文
『IC Design of Low-power Analog LDPC Decoder』64


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