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研究生:陳文杰
研究生(外文):Wen-Chieh Chen
論文名稱:高硬體效率可重組式硬體架構影像增強演算法設計
論文名稱(外文):A new hardware-efficient algorithm and reconfigurable architecture for image contrast enhancement
指導教授:黃士嘉黃士嘉引用關係李宗演李宗演引用關係
指導教授(外文):Shih-Chia HuangTrong-Yen Lee
口試委員:蔡偉和郭斯彥
口試委員(外文):Wei-Ho Tsai郭斯彥
口試日期:2012-07-04
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:英文
論文頁數:33
中文關鍵詞:影像對比度增強可重組式架構
外文關鍵詞:Image contrast enhancementreconfigurable architecture
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在高品質數位影像處理的應用如數位影像或是影片拍攝、液晶螢幕顯示器處理與醫療影像分析裡,影像對比度增強扮演著一個很重要的角色。為了使高解析度的影像應用可以達到即時影像處理,必須要設計一個有效率的影像增強硬體架構來達到即時影像處理。因此本論文提出了一個新式的硬體導向之對比度增強演算法來有效的實現硬體設計。針對硬體實現的考量,本論文提出近似法來節省演算法裡計算複雜度較高的式子。經由人因測試與數據實驗表示本論文所提出的硬體導向的對比度增強演算法能夠達到良好的影像品質。為了達到硬體及時運算的效能,我們提出了以參數控制為導向之可重組式架構來增進硬體的利用率以及節省電路面積進而降低硬體實現成本。實驗結果表示本論文所提出的硬體導向之影像對比度演算法在影像解析度為1920×1080時能夠達到每秒48.23幅之運算速度,這代表著本論文所提出的硬體架構能夠實現即時數位影像處理系統。

Contrast enhancement is crucial when generating high quality images for image processing applications such as digital image or video photography, LCD processing, and medical image analysis. In order to achieve real-time performance for high-definition video applications, it is necessary to design efficient contrast enhancement hardware architecture to meet the needs of real-time processing. In this paper, we propose a novel hardware-oriented contrast enhancement algorithm which can be implemented effectively for hardware design. In order to be considered for hardware implementation, approximation techniques are proposed to reduce these complex computations during performance of the contrast enhancement algorithm. The proposed hardware-oriented contrast enhancement algorithm achieves good image quality by measuring the results of qualitative and quantitative analyses. To decrease hardware cost and improve hardware utilization for real-time performance, a reduction in circuit area is proposed through use of parameter-controlled reconfigurable architecture. The experiment results show that the proposed hardware-oriented contrast enhancement algorithm can provide an average frame rate of 48.23 fps at high definition resolution 1920×1080. This means that the proposed hardware architecture can run in real-time.

中文摘要 i
ABSTRACT ii
誌謝 iii
CONTENTS iv
LIST OF TABLES v
LIST OF FIGURES vi
Chapter 1 INTRODUCTION 1
Chapter 2 PROPOSED ALGORITHM 4
2.1 Contrast Enhancement Algorithm 4
2.2 Hardware Implementation Consideration 6
2.2.1 Hardware consideration of log_2 k 8
2.2.2 Newton''s Divided Difference Interpolation Formula 8
2.2.3 Hardware consideration of 2^k 9
2.3 Hardware-Efficient Contrast Enhancement Algorithm 10
Chapter 3 HARDWARE ARCHITECTURE DESIGN 12
3.1 Implementation of the ISC module 14
3.2 Implementation of the WDF, SCDF, and AGC modules 14
3.2.1 Implementation of the log_2 k module and 2^k module 14
3.2.2 Implementation of Reconfigurable Structure 15
3.3 Implementation of Half Histogram Design 16
3.4 Implementation of FLT module 16
Chapter 4 EXPERIMENTAL RESULTS 19
4.1 Image Quality Comparison 19
4.1.1 Visual Assessment 19
4.1.2 Comparison 25
4.1.3 Qualitative Evaluation 26
4.2 Specification and FPGA Implementations 27
4.3 Analysis of Hardware Utilization 29
4.4 Analysis of Processing Time Reduction 30
Chapter 5 CONCLUSIONS 31
REFERENCES 32


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