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研究生:鄭詠仁
研究生(外文):Yong-Ren Jheng
論文名稱:三閘極奈米線SONOS薄膜電晶體記憶體之低頻雜訊分析
論文名稱(外文):Low-Frequency Noise in Poly-Si TFT SONOS Memory with a Tri-gate Nanowire Structure
指導教授:胡心卉
指導教授(外文):Hsin-Hui Hu
口試委員:范育成黃國威吳永俊
口試委員(外文):Yu-Cheng FanGuo-Wei HuangYung-Chun Wu
口試日期:2012-06-29
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:44
中文關鍵詞:低頻雜訊奈米線多晶矽-氧化矽-氮化矽-氧化矽-多晶矽多晶矽薄膜電晶體三閘極
外文關鍵詞:LFNnanowireSONOSpoly-Si TFTtri-gate
相關次數:
  • 被引用被引用:1
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非揮發性記憶體(nonvolatile memory, NVM)近幾年被廣泛應用在各種可攜式電子產品中。因其具有非揮發及低功耗特性,故可應用於系統整合型面板(system-on-panel, SOP)上。本論文採用之結構為具有三閘極奈米線的SONOS-TFT記憶體。其結構展現了相當優異的電性與NVM特性。近年來隨著元件尺寸微縮,使得低頻雜訊(Low-frequency noise)的影響逐漸顯著。因此本論文主要在探討具多重奈米線通道與傳統單通道元件,在Fowler–Nordheim (F-N)寫入/抹除操作前、後之低頻雜訊特性與變化。並於實驗中藉由粹取及探討晶粒邊界陷阱密度(Grain Boundary Trap density, QT)來輔助分析低頻雜訊的改變。此外,實驗中也探討在不同的寫入/抹除操作電壓下的低頻雜訊變化。藉由本論文之研究,能夠對於三閘極奈米線SONOS薄膜電晶體記憶體的設計提供有力之依據,以優化記憶體達到降低低頻雜訊的影響,進而達成實現系統面板之願景。

In recent years, nonvolatile memory (NVM) is extensively utilized in various portable electronic products. NVM can be applied to system-on-panel (SOP) applications because of its characteristics of non-volatility and low power consumption. In this thesis, the NVM utilizes a silicon-oxide-nitride-oxide-silicon (SONOS)-type thin-film transistor (TFT) with a tri-gate multiple nanowire (NW) channels, which has shown excellent electrical and NVM characteristics. The impact of low-frequency noise (LFN) gets more severe derived from the pursuit of smaller size of devices these days. In this case, we would like to study the characteristics and changed phenomenon of LFN in multiple NW and a standard single-channel (SC) SONOS-TFTs under Fowler–Nordheim tunneling program/erase (P/E) operation. In addition, we also analyzed LFN by extracting and studying Grain boundary trap density (QT) in the process as assistant. Besides, the relationship of P/E operation voltage and LFN would be discussed as well. In conclusion, through this thesis, we would like to provide trigate nanowire SONOS-TFT design with strong reference to optimize memory by reducing the impact of LFN, and thus achieve the idealization of SOP.

摘要 i
ABSTRACT ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 序論 1
1.1 研究背景 1
1.2 研究動機 4
1.3 論文綱要 4
第二章 SONOS記憶體架構與低頻雜訊基礎理論 6
2.1 SONOS快閃記憶體的結構 6
2.2 低頻雜訊形成機制與概論 8
2.2.1 熱雜訊(Thermal noise) 9
2.2.2 散射雜訊(Shot noise) 9
2.2.3 產生-複合雜訊(Generation-Recombination noise)與勞倫茲
頻譜 (Lorentzian spectrum) 10
2.2.4 閃爍雜訊(Flicker noise) 11
2.2.5 隨機電報雜訊(Random Telegraph noise, RTN) 11
2.3 1/f雜訊模型 12
2.3.1 載子數目擾動(Number fluctuation) 12
2.3.2 遷移率擾動(Mobility fluctuation) 14
2.3.3 相關遷移率擾動(Correlated mobility fluctuation) 15
第三章 三閘極奈米線結構的SONOS-TFT記憶體之低頻雜訊分析 16
3.1 實驗背景 16
3.2 實驗方法 16
3.2.1 元件結構 16
3.2.2 實驗設備及量測方式 18
3.2.3 元件製程 19
3.3 實驗結果與討論 19
3.3.1 低頻雜訊結果與討論 19
3.3.2 隨機電報雜訊結果與討論 22
3.3.3 1/f雜訊模型分析 23
3.4 實驗結論 25
第四章 三閘極奈米線結構的SONOS-TFT記憶體在Program/Erase操作
前後之低頻雜訊分析 26
4.1 實驗背景 26
4.2 實驗方法 26
4.2.1 元件結構 26
4.2.2 實驗設備及量測方式 27
4.3 實驗結果與討論 28
4.3.1 晶粒邊界陷阱密度結果與討論 28
4.3.2 低頻雜訊結果與討論 32
4.3.3 1/f雜訊模型分析 35
4.4 實驗結論 37
第五章 結論與未來研究方向 38
5.1 結論 38
5.2 未來研究方向 38
參考文獻 40


[1]T. Nishibe and H. Nakamura, “Value-Added Circuit and Function Integration for SOG (System-on Glass) Based on LTPS Technology”, SID Tech. Dig., 2006, pp. 1902-1904.
[2]K. Kim,“Technology for sub 50 nm node DRAM and NAND Flash Manufacturing,” IDEM Tech. Digest, 2005, pp. 333-336.
[3]E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, S. C. Lee, C. P. Lu, S. Y. Wang, L. W. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, J. Ku, R. Liu, and C. Y. Lu, “A Highly Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” VLSI Technology Symposium, 2006, pp. 56-57.
[4]Andrew J. Walker, Sucheta Nallamothu, En-Hsing Chen, Maitreyee Mahajani, S. Brad Hemer, Mark Clark, James M. Cleeves, S. Vance Dunton, Victoria L. Eckert, James Gu, Susan Hu, Johan Knall, Michael Konevecki, Christopher Petti, Steven Radigan, Usha Raghuram, Joetta Vienna, and Michael A. Vyvoda, “3D TFT-SONOS Memory Cell for Ultra-High Density File Storage Applications,” VLSl Technology Digest, 2003, pp. 29-30.
[5]Y. H. Lin, C. H. Chien, T. H. Chou, T. S. Chao, and T. F. Lei, “Low-Temperature Polycrystalline Silicon Thin-Film Flash Memory With Hafnium Silicate,” IEEE Trans. Electron Devices, vol. 54, no. 3, 2007, pp. 531-536.
[6]Marvin H. White, D.A. Adams, and J. Bu, “On the go with SONOS,” IEEE CIRCUIT & DEVICE, 2000, pp. 22.
[7]Szu-I Hsieh, Hung-Tse Chen, Yu-Cheng Chen, Chi-Lin Chen, and Ya-Chin King, “MONOS Memory in Sequential Laterally Solidified Low-Temperature Poly-Si TFTs,” IEEE Electron Device Lett., vol. 27, no. 4, 2006, pp. 272-274.
[8]Yung-Chun Wu, Po-Wen Su, Chin-Wei Chang, and Min-Feng Hung, “Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure,” IEEE Electron Device Lett., vol. 29, no. 11, 2008, pp. 1226-1228.
[9]Min-Feng Hung, Yung-Chun Wu, and Jiang-Hung Chen, “2-bit operation based on modulated Fowler-Nordheim tunneling in charge-trapping flash memory cell,” Appl. Phys. Lett., vol. 100, no. 5, 2012, pp. 052107-052107-3.
[10]Yung-Chun Wu, Chun-Yen Chang, Ting-Chang Chang, Po-Tsun Liu, Chi-Shen Chen, Chun-Hao Tu, Hsiao-Wen Zan, Ya-Hsiang Tai, and Simon Min Sze, “High Performance and High Reliability Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels,” IEDM Technical Digest, 2004, pp. 777-780.
[11]C. T. Angelis, C. A. Dimitriadisa, F. V. Farmakis, J. Brini, G. Kamarinos, and M. Miyasaka, “Dimension scaling of low frequency noise in the drain current of polycrystalline silicon thin-film transistors,” Journal of Applied Physics, vol. 86, no. 12, 1999, pp. 7083-7086.
[12]Rock-Hyun Baek, Chang-Ki Baek, Sung-Woo Jung, Yun Young Yeoh, Dong-Won Kim, Jeong-Soo Lee, Kim, D.M., and Yoon-Ha Jeong, “Characteristics of the Series Resistance Extracted From Si Nanowire FETs Using the-Function Technique,” IEEE Transactions On Nanotechnol., vol. 9, no. 2, 2010, pp. 212-217.
[13]Jing Zhuge, Runsheng Wang, Ru Huang, Yu Tian, Liangliang Zhang, Dong-Won Kim, Donggun Park, Yangyuan Wang , “Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs,” IEEE Electron Device Letters, vol. 30, no. 1, 2009, pp. 57-60.
[14]Chengqing Wei, Yu Jiang, Yong-Zhong Xiong, Xing Zhou, N. Singh, S.C. Rustagi, Guo Qiang Lo, and Dim-Lee Kwong, “Impact of Gate Electrodes on 1/f Noise of Gate-All-Around Silicon Nanowire Transistors,” IEEE Electron Device Letters, vol. 30, no. 10, 2009, pp. 1081-1083.
[15]C.T. Angelis, C.A. Dimitriadis, J. Brini, G. Kamarinos, V.K. Gueorguiev, T.E. Ivanov, “Low-frequency noise spectroscopy of polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 46, no. 5, 1999, pp. 968-974.
[16]Charalabos A. Dimitriadis, Jean Brini, and George Kamarinos, “Origin of low frequency noise in polycrystalline silicon thin-film transistors,” Thin Solid Films, vol. 427, no. 1-2, 2003, pp. 113-116.
[17]M. Behravan and D. T. Story, “Noise Characterization of n- and p-Type Polycrystalline-Silicon Thin-Film Transistors,” IEEE Transactions on Device and Materials Reliability, vol. 9, no. 3, 2009, pp. 327-328.
[18]N. Tega, H. Miki, T. Osabe, A. Kotabe, K. Otsuga, H. Kurata, S. Kamohara, K. Tokami, Y. Ikeda, R. and Yamada, “Anomalously Large Threshold Voltage Fluctuation by Complex Random Telegraph Signal in Floating Gate Flash Memory,” IEDM Technical Digest, San Francisco, CA, 2006, pp. 1-4.
[19]Sing-Rong Li, W. McMahon, Y.-L.R. Lu, and Yung-Huei Lee, “RTS Noise Characterization in Flash Cells,” IEEE Electron Device Lett., vol. 29, no. 1, 2008, pp. 106-108.
[20]Yung-Chun Wu, Ting-Chang Chang, Chun-Yen Chang, Chi-Shen Chen, Chun-Hao Tu, Po-Tsun Liu, Hsiao-Wen Zan, and Ya -Hsiang Tai, “High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure,” Applied Physics Letters, vol. 84, no. 19, 2004, pp. 3822-3824.
[21]Yu-Hsien Lin, Chao-Hsin Chien, Tung-Huan Chou, Tien-Sheng Chao, Tan-Fu Lei, “Impact of Channel Dangling Bonds on Reliability Characteristics of Flash Memory on Poly-Si Thin Films,” IEEE Electron Device Lett., vol. 28, no. 4, 2008, pp. 267-269.
[22]G. Krause, K.R. Hofmann,and M.F. Beug, “1/f Noise Analysis of a 75 nm Twin-FlashTM Technology Non-Volatile Memory Cell,” NVMTS 7th, San Mateo, CA, 2006, pp. 12-15
[23]Hao D. Xiong, Wenyong Wang, Qiliang Li, Curt A. Richter, John S. Suehle1, Woong-Ki Hong, Takhee Lee, and Daniel M. Fleetwood, “Random telegraph signals in n-type ZnO nanowire field effect transistors at low temperature,” Appl. Phys. Lett. vol. 91, no. 5, 2007, pp. 053 107-1-053 107-3.
[24]A. Van der Ziel, Noise in Solid State Devices and Circuits, New York: Wiley, 1986.
[25]A. Van Der Ziel, E.R., and Chenette, “Advances in Electronics and Electron Physics,” Adv. Electron. Electron Phys, vol. 46, 1978, pp. 313.
[26]Martin von Haartman and Mikael Ostling, Low-Frequency Noise in Advanced MOS Devices, New York: Springer Publishing Company, 2007, pp. 1-101.
[27]H. Nyquist, “Thermal agitation of electric charge in conductors,” Physical Review, vol. 32, 1928, pp. 110.
[28]Wong Hei, “Low-frequency noise study in electron devices: review and update,” Microelectronics Reliability, vol. 43, no. 4, 2003, pp. 585-599.
[29]C. Surya, T.Y. Hisang, “Surface mobility fluctuations in metal oxide semiconductor field effect transistors,” Physical review B, vol. 35, no. 12, 1987, pp. 6343-6347.
[30]Kwok K. Hung, Ping K. Ko, Chenming Hu, and Yiu C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,” IEEE Trans. Electron Devices, vol. 37, no. 3, 1990, pp. 654-665.
[31]M.E. Welland, R. H. Koch, “Spatial location of electron trapping defects on silicon by scanning tunneling microscopy,” Applied physics letters, vol. 48, no. 11, 1986, pp. 724-726.
[32]K. S. Ralls, W. J. Skocpol, L.D. Jackel, R.E. Howard, L.A. Fetter, R.W. Epworth, and D.M. Tennant, “Discrete Resistance Switching in Submicrometer Silicon Inversion Layers: Individual Interface Traps and Low Frequency (1/f) Noise,” Physical review letters, vol. 52, no. 3, 1984, pp. 228-231.
[33]G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations inadvanced CMOS devices,” Microelectron. Reliab., vol. 42, no. 4, 2002, pp. 573-582.
[34]A. Corradetti, R. Leoni, R. Carluccio, G. Fortunato, C. Reita, F. Plais, and
D. Pribat, “Evidence of carrier number fluctuation as origin of 1/f noise
in polycrystalline silicon thin film transistors,” Applied Physics Letters, vol. 67, no. 12, 1995, pp. 1730-1732.
[35]J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” Journal of Applied Physics, vol. 53, no. 2, 1982, pp. 1193-1202.
[36]Sung-Min Joe, Jeong-Hyong Yi, Sung-Kye Park, Hyungcheol Shin, Byung-Gook Park, Young June Park, Jong-Ho Lee, “Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String,” IEEE Transactions on Electron Devices, vol. 58, no. 1, 2011, pp.67-73.
[37]S. C. Chen, T. C. Chang , P. T. Liu, Y. C. Wu, J. Y. Chin, P. H. Yeh, L. W. Feng, S. M. Sze, C. Y. Chang, and C. H. Lien, “Nonvolatile Si/SiO2/SiN/SiO2/Si type polycrystalline silicon thin-film-transistor memory with nanowire channels for improvement of erasingcharacteristics,” Appl. Phys. Lett., vol. 91, no. 19, 2007, pp.193103-193103-3.
[38]Corradetti, R. Leoni, R. Carluccio, G. Fortunato C. Reita, F. Plais, and D. Pribat, “Evidence of carrier number fluctuation as origin of 1/f noise in polycrystalline silicon thin film transistors,” Appl. Phys. Lett., vol. 67, no. 12, 1995, pp. 1730-1732.
[39]R.E. Proano, R.S. Misage, D.G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 36, no. 9, 1989, pp. 1915-1922.
[40]A. Fayrushin , K. Seol , J. Na , S. Hur , J. Choi, and K. Kim, “The new program/erase cycling degradation mechanism of NAND Flash memory devices”, in IEDM Tech. Dig., 2009, pp. 823-826.
[41]C. A. Dimitriadis, F. V. Farmakis, G. Kamarinos, and J. Brini, “Origin of low-frequency noise in polycrystalline silicon thin-film transistors,” J. Appl. Phys., vol. 91, no. 12, 2002, pp. 9919-9923.


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