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研究生:林世偉
研究生(外文):Shih-Wei Lin
論文名稱:基於SOPC平台之JPEG-LS影像編解碼系統設計
論文名稱(外文):The Implementation of a JPEG-LS Codec System based on the SOPC Platform
指導教授:高立人高立人引用關係
口試委員:林國祥王多柏李宗演
口試日期:2012-07-12
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:105
中文關鍵詞:JPEG-LSFPGA軟硬體協同設計管線處理
外文關鍵詞:JPEG-LSFPGAHardware and software codesignPipeline processing
相關次數:
  • 被引用被引用:0
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JPEG-LS是非失真以及近乎非失真影像壓縮的國際標準。本論文主要針對非失真模式提出一高效能之JPEG-LS編解碼電路並以軟硬體協同技術將其實現於FPGA。其中編碼器是以管線之架構來設計,而解碼器則是利用軟硬體協同運算的方式設計。為了驗證所設計之編解碼器,我們將編碼器與解碼器分別實現於ALTERA之FPGA 中。所規劃之編碼器電路時脈可以達到113.03MHz,瞬間產出量也可達到113.03MPixel/s,解碼器電路時脈則可以達到105.21MHz。為了驗證本電路之可用性,本論文也實際設計了一套完整的雲端影像編解碼系統,使用者僅需利用可上網之設備,即可透過網頁取得非失真編解碼與儲存之服務。經由各項實驗證明,本研究所提出的電路架構不論在瞬間產出量、使用面積與記憶體使用量等方面均有不錯的表現。

JPEG-LS is a coding standard for lossless and near-lossless image compression formulated by ITU/ISO. In this thesis, a high performance codec system is proposed and implemented in FPGA for the regular mode in the lossless scheme of JPEG-LS. The encoder is designed by using a pipeline architecture, while the decoder is based on hardware and software codesign. In order to verify the correctness and performance of the proposed codec, the encoder and decoder are implemented in the ALTERA FPGA respectively. The frequency of the proposed encoder circuit can have a clock rate up to 113.03MHz, and the throughput can be up to 113.03MPixel/s. The frequency of the proposed decoder can be up to 105.21MHz. In addition to the proposed codec circuits, we also implement a cloud-based image codec system in this thesis so that the usefulness of the proposed architecture can be demonstrated. In the proposed cloud-based codec system, only a browser is needed for accessing the service of image coding and decoding on the Internet. As we can see in the experiment, the proposed architecture can have a very good performance in terms of throughput, chip area, memory usage, and outperforms existing state-of-the-art JPEG-LS codecs.

摘 要 i
ABSTRACT ii
誌 謝 iii
目 錄 iv
表目錄 viiii
圖目錄 ixx
第一章 緒論 1
1.1 研究動機 1
1.2 文獻回顧 2
1.3 研究貢獻 3
1.4 論文大綱 4
第二章 JPEG-LS演算法 5
2.1 JPEG-LS 5
2.1.1 參數定義與初始化 6
2.1.2 編碼流程決策 (Mode Decision) 7
2.1.3梯度量化與Context決策 (Gradient Quantization & Context Decision) 9
2.1.4 邊界偵測器 (Median Edge Detector) 10
2.1.5 預測修正與預測誤差計算 (Prediction Correction & Computation of Prediction Error) 11
2.1.6 誤差範圍修正與誤差映射 (Error Remapping & Error Mapping) 12
2.1.7 誤差編碼 (Error Encoding) 13
2.1.8 Context更新 (Context Update) 13
2.1.9 補償值計算 ( Bias Computation) 14
2.1.10 掃描像素點 (Run Scanning) 15
2.1.11編碼掃描數量 (Run-Length Coding) 16
2.1.12 Run Mode中斷 (Run Interrupt) 17
2.2 JPEG-LS分析 19
第三章 編解碼電路架構 23
3.1 Context 記憶體 23
3.2 編碼電路 26
3.2.1 編碼器之Context記憶體 28
3.2.2 編碼器Stage 1 28
3.2.3 編碼器Stage 2 31
3.2.4 編碼器Stage 3 31
3.2.5 編碼器Stage 4 32
3.2.6 編碼器Stage 5 32
3.2.7 編碼器Stage 6 33
3.2.8 編碼器Stage 7 33
3.2.9 編碼器Stage 8 34
3.2.10 編碼器Stage 9 36
3.2.11 編碼器Stage 10 39
3.2.12 編碼器Stage 11 41
3.2.13 編碼器Stage 12 41
3.2.14 編碼器Stage 13 42
3.3 解碼電路 45
3.3.1 解碼器Stage 5 46
3.3.2 解碼器Stage 6 46
3.3.3 解碼器Stage 7 47
3.3.4 解碼器Stage 8 47
3.3.5 解碼器Stage 9 47
3.3.6 解碼器Stage 10 51
3.3.7 解碼器Stage 11 53
3.3.8 解碼器Stage 12 54
第四章 系統實作 55
4.1 編解碼電路驗證 55
4.1.1 產生M4K記憶體區塊 55
4.1.2 Modelsim驗證 57
4.2開發流程 59
4.3 開發平台 60
4.4 SOPC系統 61
4.4.1. Nios II處理器 63
4.4.2 Avalon Bus IP 67
4.4.2.1 編碼器 IP 69
4.4.2.2編碼器 IP 70
4.4.3 Zip File System & Host File System 72
4.5 雲端影像編解碼系統 73
4.5.1 醫療院所之雲端架構 73
4.5.2 編解碼流程 74
4.5.3 整合SOPC 76
4.5.4 Nios II設定 78
4.5.5 移植uClinux 78
4.5.6 PHP & MySQL 81
第五章 實驗結果 89
5.1 編解碼電路 89
5.1.1 正確性驗證 89
5.1.2 複雜度分析 90
5.1.2.1 空間複雜度 90
5.1.2.2 時間複雜度 92
5.2 雲端編解碼系統 93
5.3 編碼電路效能比較 96
第六章 結論與未來展望 100
6.1 結論 100
6.2未來展望 101
參考文獻 102


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