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研究生:黃政德
研究生(外文):Cheng-De Huang
論文名稱:應用於晶片網路之低功率網路介面設計
論文名稱(外文):Design of a Low Power Network Interface for Network-on-Chip
指導教授:李宗演李宗演引用關係
口試委員:熊博安蔡加春
口試日期:2012-06-28
學位類別:碩士
校院名稱:國立臺北科技大學
系所名稱:電腦與通訊研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:44
中文關鍵詞:晶片網路網路介面時脈閘控功率消耗
外文關鍵詞:NoCNetwork InterfaceClock GatingPower Consumption
相關次數:
  • 被引用被引用:1
  • 點閱點閱:127
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  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
近年來多核心運算架構常使用於晶片系統(System-on-Chip, SoC)中。由於晶片系統中包含多個處理單元(Processing Elements, PEs)以及相對應的互連結構,各處理單元之間訊息交換相當頻繁導致功率消耗與資料延遲問題,因此有許多研究提出晶片網路(Network-on-Chip, NoC)的方法,使得低功率高效能的設計也變成了重要的議題。若能移除在序向電路(Sequential Circuit)中不必要的切換動作(Switching Activity),將能大幅度減少功率消耗。在本篇論文提出應用於晶片網路之網路介面時脈閘控架構設計來改善網路介面中緩衝器的功率損耗。因傳送大量資料導致FIFO在Full與Empty狀態下等待讀取時間不短,若能使緩衝器進入休眠(Shut Down)狀態,並且改善其有限狀態機(Finite State Machine)的狀態策略,而利用時脈閘控技術將不必要時脈去掉,則可有效降低緩衝器功率消耗。由實驗結果得知,本文所提出的網路介面之時脈閘控架構中增加少許硬體資源,最大可降低30%功率消耗。

In recent years, multi-core computing architectures have been used in System-on-Chip (SoC), which contains multiple processing elements and corresponding, interconnects structure. Messages are switched among the processing elements quite frequently. Therefore, the data latency and power consumption issues are generated. Many studies have proposed to solve those issues in a Network-on-Chips (NoC). If the function unit to remove unnecessary switching activity, it dramatically reduce power consumption degree. This work proposes Clock Gating Circuit (CGC) architecture to reduce the power consumption in Network-on-chip. When buffer state is full or empty, the proposal circuit will gate buffer period to reduce power consumption. The experimental results show that the proposed Clock-Gating technique can maximum reduces 30% power consumption under increasing a few hardware resources.

中文摘要i
英文摘要ii
誌謝iii
目錄iv
表目錄v
圖目錄vi
第一章 緒論1
1.1 簡介1
1.2 研究動機與目的1
1.3 本論文貢獻2
1.4 論文架構2
第二章 相關文獻探討 3
2.1 晶片網路研究與架構4
2.1.1 晶片網路拓樸架構4
2.1.2晶片網路上的交換技術10
2.1.3繞徑演算法14
2.2應用於晶片網路介面相關研究15
第三章 低功率網路介面設計22
3.1定義拓樸與封包架構23
3.2網路介面電路架構設計26
3.3 Shell與Kernel模組時脈閘控策略設計29
3.4 Header & Payload Memory時脈閘控策略設計33
第四章 實驗結果37
4.1 功率消耗估算說明37
4.2 實驗結果與分析39
第五章 結論與未來工作42
參考文獻43



[1]L.Benini and G. De Michei, “Network on chips: a new SoC paradigm,” IEEE Transactions on Computer, vol. 35, no. 1, January 2002, pp. 70-78.
[2]F. KARIM, A. NGUYEN, and S. DEY, “An interconnect architecture for networking system on chip,” IEEE Transactions on Micro, vol. 22, no. 5, pp. 36-45, Sep. 2002.
[3]H.C. Fritas, T.G.S. Santos, and P.O.A. Navaux, “Design of programmable NoC router architecture on FPGA for multi-cluster NoCs,” Electronics Letter, vol. 44, no. 16, pp. 969-971, Jul. 2008.
[4]H. C. Chi and J. H. Chen, “Design and implementation of a routing switch for on chip interconnection network,” in Proc. of IEEE Asia-Pacific conference on Advanced System Integrated Circuits, Fukuoka, Japan, Aug. 2004, pp. 392-395.
[5]S. Santi, B. Lin, L. Kocarev, G. M. Maggio, R. Rovatti, and G. Setti, “On the impact of traffic statistics on quality of service for network on chip,” in Proc. of IEEE International Symposium on Circuits and Systems, May 2005, pp. 2349-2352.
[6]C. M. Wu and H. C. Chi, “Design of a high performance switch for circuit switched on chip networks” in Proc. of IEEE Asian Solid-State Circuits Conference, Taiwan, Nov. 2005, pp. 481-484.
[7]K. Goossens, J. Dielissen and A. Radulescu, “Atheral Network on Chip:Concepts, Architectures, and Implementations,” IEEE Design and Test of Computers, vol. 22, no. 5, September 2005, pp. 21-31.
[8]S. Saponara, L. Fanucci, and M. Coppola “Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects,” Journal of Microprocessors and Microsystems - Embedded Hardware Design, vol. 35, no. 6, August 2011, pp. 579-592.
[9]M. Tassori, M. Tassori, and M. Mossavi “Adaptive Data Compression for High-Performance Low-Power On-Chip Networks,” Journal of Internation Review on Computer and Software, vol. 5, no. 5, September 2010, pp. 540-547.
[10]http://www.xilinx.com, “Xilinx Reducing Switching Power with Intelligent Clock Gating,” WP370 (v1.3), March 1, 2011.
[11]C. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, V. Narayanan, C. Das and M. Irwin, “On the Effects of Process Variation in Network-on-Chip Architectures,” Journal of IEEE Transactions on Dependable and Secure Computing, vol. 7, no. 3, 2010, Article number 4663075, pp. 240-254.
[12]黃啟翰,應用於晶片網路之緩衝器時脈閘控架構設計,碩士論文,國立臺北科技大學電腦與通訊研究所,臺北,2011。
[13]B. Attia, W. Chouchene, A. Zitouni, N. Abid, and R. Tourki, “Design and Implementation of Low Latency Network Interface for Network on chip,” in Proc. 5th Int. Design and Test Workshop (IDT), March 2010, pp. 37-42.
[14]B. Attia, A. Zitouni, and R. Tourki, “Design and Implementation of Network Interface Compatible OCP for Packet Based NoC,” in Proc. 5th Int. Design & Technology of Integrated System in Nanoscale Era (DTIS), March 2010, pp. 1-8.
[15]W. Chouchene, B. Attia, A. Zitouni, N. Abid, and R. Tourki, “A Low Power Network Interface For Network on chip,” in Proc. 8th Int. Multi-conference on System, signals & Devices, May 2011, pp. 1-6.
[16]http://www.xilinx.com, “Xilinx XPower Tutorial,” UG733 (v1.0), March 15, 2010.


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