臺灣博碩士論文加值系統

本篇文章中的研究重點，主要是針對以10GT/s以上速率(40GT/s, 100GT/s…等等)傳輸，同時又需要克服5m~10m傳輸距離的高速通訊系統，在尋找傳輸時通訊晶片中等化器的參數設定上，能更為快速且有效。現今電信網路的骨幹，都以10Gbit/s以上的速率傳輸，但因為傳輸距離本身造成的物理限制，在為了保持良好的訊號完整性的要求下，常常需要應用到等化器的設計。在傳輸架構中，如何設定等化器也是一個很關鍵的因素。系統工程師必須針對不同的傳輸距離，路徑中不同種類與數量的連接器，以及纜線等元素共同組成的通道特性搭配等化器的架構，來找出最佳的等化器參數設定值。但是，因為等化器的結構與矽智財產權相關，晶片設計者普遍傾向不提供等化器的架構給系統設計者，而以數學模型取代。在如此條件限制下，系統設計者在缺乏明確的尋找方向時，以針對參數做完整掃瞄的方式去尋找最佳值時，不但曠日費時，且不一定能在有限的時間內找到最佳的等化器設定值。這裡將研究一種方法，尤其針對擁有越多可設定等化器參數的設計時，越能發揮優勢。例如在一個擁有四個可設定之等化器參數的設計中，本文中介紹的方法將會具有比傳統完整掃瞄的方法加速二十七倍的優勢。

Hereby I proposed to study a method, especially for digital communication systems which are operated above 10GT/s (40GT/s , 100GT/s…etc) rate with 5m~10m transmission distance, to optimize the setting of the communication IC’s equalizer faster and more efficiently. Nowadays, in the main frame of telecomm network, due to the high bit rate and the physical limit caused by the long transmission distance, we usually include equalizer into our circuit design to ensure a good signal quality. Still, how to set the equalizer’s tap coefficient is another critical factor for communication system. System engineers need to find out the optimized setting of the equalizer’s tap coefficient according to the architecture of the telecom IC’s equalizer against the property of communication channel which consist of paths in different lengths, connectors of different types, and cables. But because the architecture of equalizer is heavily related to silicon intelligent property, generally, the IC designers tend to give the mathematical model instead of the equalizer’s architecture to the system designers. Due to this limit for lack of clear and definite direction to find out the optimized setting of equalizer’s tap coefficient, system designers will take much more time to do a full sweep against all parameter but still fail to find out the optimized setting in a certain limited period. The method studied hereby, especially for designing equalizers with more tap coefficient, can have more advantage in time. For example, in a 4-bit equalizer optimization, using this method will be 27 times faster than a full sweep against all four taps of the equalizer.

摘　要 ii
ABSTRACT iii
誌　謝 v
表目錄 viii
圖目錄 ix
第一章 緒 論 1
1.1 前言 1
1.2研究動機與目的 1
1.3研究方法與章節介紹 3
第二章 基本理論簡介 4
2.1 最適性等化器(ADAPTIVE EQULAIZER) 4
2.1.1 等化器架構與高速數位通訊系統架構 4
2.1.2 最小平方誤差方法(Minimum Square Error) 6
2.1.3 最陡下降方法(Steepest Descend Method) 10
2.2 最適性等化器設計範例 11
第三章 二等分法 16
3.1 討論指標(INDICATOR)的切換 16
3.2 二等分法的內容與操作 18
3.3 二等分法的流程圖 24
第四章 實際案例的驗證 25
4.1IBIS-AMI模型格式 25
4.2 案例一-10GBASE-KR訊號傳輸通道 28
4.2.1 操作過程 28
4.2.2 驗證 35
4.3 案例二-XFI訊號傳輸通道 38
4.3.1 操作過程 38
4.3.2 驗證 43
第五章 結 論 48
參考文獻 50
附錄 52
A. EXAMPLE 1所使用的印刷電路板 52
B. EXAMPLE 2所使用的印刷電路板 53

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