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研究生:朱汶鈺
研究生(外文):Wen-Yu Chu
論文名稱:具有誤差修正功能之快速鎖定責任週期校正器
論文名稱(外文):A Fast-Locking Duty Cycle Corrector With Deskew Capability
指導教授:黃崇禧
指導教授(外文):Chorng-Sii Hwang
學位類別:碩士
校院名稱:國立雲林科技大學
系所名稱:電機工程系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:100
語文別:中文
論文頁數:81
中文關鍵詞:週期性時間數位轉換器快速鎖定同步計數器漸進比較式搜尋控制器
外文關鍵詞:Successive Approximation RegisterFast-LockingSynchronous AdderCyclic Time-to-Digital Converter
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本篇論文提出一個快速鎖定、架構簡易的全數位責任週期校正器。其責任週期校正的方式是使用兩個半延遲線(Half Delay Line)的架構,利用在時脈相位鎖定後,一個半延遲線的延遲時間剛好會等於輸入時脈週期一半的特性,因此便可將輸出時脈責任週期校正為50%;並利用另外一個半延遲線以解決輸出與輸入時脈的相位誤差 (Skew)的問題。

本論文提出一個具有計數功能的漸進比較式搜尋控制器,此為一般的傳統漸進比較式搜尋控制器(Successive Approximation Register ,SAR) 結合同步加法器(Synchronous Adder),故可將漸進比較式搜尋控制器所產生的控制碼更簡易得載入至同步加法器,此方法使電路更簡單又不需要額外的暫存器,可節省掉許多面積。

實際電路以TSMC 0.18μm 1P6M 的製程實現,操作頻率為150-540MHz。時脈相位誤差校正(Deskew)可達-3.21ps~9.87ps,可校正輸入時脈15%至85%的責任週期至輸出時脈50%,且當電路定之後仍然會利用同步計數器的方式達到閉迴路控制。
In this paper, a fast-locking all-digital duty cycle corrector has simple architecture is proposed. It is using the feature of two Half Delay Line (HDL) which is a delay of HDL is equal to a half of input clock period for correcting the output clock duty cycle to 50%. And then, it could set the other Half Delay Line to decrease the phase error between input and output clock.

In order to load the controlled code of Successive Approximation Register to the Synchronous Adder easily, a Hybrid-SAR was proposed combining the Successive Approximation Register with Up/Down Counter to reach to simple architecture without extra circuits and small area.

A test chip was fabricated in TSMC 0.18-μm 1P6M technology. The circuit can operate at the input clock from 150 to 540 MHz, and tolerate the input duty cycle variation from 15% to 85% to generate 50% output clock with the skew within -3.21ps ~ 9.87ps. It adopts Synchronous Adder to reach close-loop controlled as the system has been locked.
中文摘要
Abstract
致謝
目錄
表目錄
圖目錄
第一章 緒論
1.1 動機
1.2 電路設計流程
1.3 論文架構
第二章 延遲鎖定迴路
2.1 類比式延遲鎖定迴路簡介
2.2 數位式延遲鎖定迴路
2.2.1 移位暫存器式
2.2.2 計數器式
2.2.3 漸進比較式
2.2.4 時間至數位轉換式
2.3 比較與整理
2.4 工作週期修正電路
第三章 具有誤差修正功能之快速鎖定責任週期校正器
3.1 架構介紹
3.2 操作原理
3.3 電路設計
3.3.1 粗調延遲線
3.3.2 細調延遲線
3.3.3 週期性時間至數位轉換器
3.3.4 邊緣合成器
3.3.5 相位偵測器
3.3.6 除頻器
3.3.7 混合式漸進比較搜尋控制器
3.3.8 狀態控制器
第四章 電路實現與模擬結果
4.1 行為模擬結果與分析
4.2 預模擬(Pre-Simulation)結果
4.2.1 半延遲線特性
4.2.2 整體架構模擬結果
4.3 電路規格與比較表
4.4 量測環境與考量
第五章 總結
結論
未來展望
參考文獻
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