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研究生:吳珮瑄
研究生(外文):Wu, Pei-Hsuan
論文名稱:含高功率二極體構裝結構之機械特性模擬分析
論文名稱(外文):Mechanical Property Analyses of the High-power Diode Package Structure
指導教授:羅本喆
指導教授(外文):Lwo, Ben-Je
口試委員:陳永樹劉錦坤
口試委員(外文):Chen, Yung-ShuLiu, Chin-Kun
口試日期:2013-05-13
學位類別:碩士
校院名稱:國防大學理工學院
系所名稱:機械工程碩士班
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:94
中文關鍵詞:二極體熱阻值熱應力
外文關鍵詞:DiodeThermal ResistanceThermo-stress
相關次數:
  • 被引用被引用:0
  • 點閱點閱:181
  • 評分評分:
  • 下載下載:5
  • 收藏至我的研究室書目清單書目收藏:1
隨著半導體元件朝著輕薄短小的趨勢下,元件構裝的散熱問題和熱應力問題也日益受到重視。構裝體在經過製造、測試及操作時,由於溫度及熱膨脹係數的不同,造成材料之間產生熱應力,這些問題對電子構裝產品而言都是需要努力去克服的。
本文利用有限元素數值模擬來分析充電器中傳統高功率二極體構裝在作用中產生的散熱特性及熱應力,採用工具則是ANSYS 13.0商業化軟體。因印刷電路板(Printed Circuit Board;PCB)結構十分複雜,為了能夠快速模擬計算其應力值,所以利用等效材料特性方程式先簡化了PCB之結構為等效材料;而整體模擬中的邊界條件則是由實驗所量測的溫度經過疊代所計算得知,並擷取充電器中高功率二極體構裝下印刷電路板之溫度和位移作為局部模擬的邊界條件。接著將構裝體詳細的內部結構建模作局部模擬分析,而後採用Z公司的新型高功率二極體構裝取代原來傳統高功率二極體構裝,並與原先的傳統構裝體作熱阻值及晶片應力分析比較。模擬結果發現新型高功率二極體構裝在熱阻值和晶片應力的表現較優於傳統高功率二極體構裝,因此可讓產品提昇可靠度。

As the trend of the semiconductor components was developed toward smaller and lighter, the thermal and thermo-stress problems on microelectronic packaging increase at the same time. Consequently, stresses are generated between the material in a packaging structure due to the differences on temperature distributions and the thermal expansion coefficient during manufacturing, testing and operation, and the problems need to be overcome for the packaging products.
This thesis uses the commercial ANSYS 13.0 finite element software to analyse the thermal and thermo-stress characteristics on high power diode packaging inside a typical power adapter. To this end, the equivalent equations to simplify the PCB(printed circuit board) material were first employed since the PCB structure is very complex. The global simulation were next performed with boundary conditions derived from iterations and verified through the comparisons with temperature measurements, and the temperature and displacement results on the PCB were then retrieved as the boundary conditions for the followed local simulations. Finally, The local models were built for both traditional diode packaging and the newly developed packaging with structure details, and thermal resistances and thermo-stresses on the models were next simulated. The results in this study shows that the newly designed packaging has better thermal resistance and smaller chip stresses than the traditional ones. Therefore, better reliability on the new packaging was verified through this work.

誌謝 ii
摘要 iii
ABSTRACT iv
目錄 v
表目錄 viii
圖目錄 ix
符號說明 xiii
1.緒論 1
1.1前言 1
1.2高功率二極體及其構裝 1
1.3研究動機與目的 3
1.4文獻回顧 3
1.5研究架構 5
2.理論分析 6
2.1熱分析 6
2.1.1傳導 6
2.1.2對流 7
2.1.3輻射 9
2.1.4熱平衡方程式 9
2.2熱應力理論分析 11
2.3等效材料分析 18
3.實驗規劃 25
3.1充電器規格介紹 25
3.2實驗儀器說明介紹 26
3.2.1溫度控制器 26
3.2.2數位電表 27
3.2.3負載台 28
3.2.4熱外線偵測儀 29
3.2.5實驗器材架設 30
3.3實驗流程 31
3.4實驗結果 31
4.研究流程與模型之建立 39
4.1研究流程 39
4.2模型之建立 41
4.2.1基本假設 41
4.2.2構裝體3D模型之建立 41
5.模擬分析結果與討論 53
5.1材料性質與邊界條件 53
5.2整體模擬分析 56
5.3局部模擬分析及比較 63
5.3.1溫度局部模擬結果 63
5.3.2應力局部模擬結果 76
6.結論與未來展望 87
6.1結論 87
6.2未來展望 87
參考文獻 89
論文發表 93
自傳 94

[1]http://www.kson.com.tw/chinese/study_15-17.htm
[2]Chow, S. G., Lin, Y., Ouyang, E., and Ahn, B., “A Finite Element Analysis of Board Level Temperature Cycling Reliability of Embedded Wafer Level BGA (eWLB) Package,” Proceeding of the 62th ECTC (Electronic Components and Technology Conference), pp. 1448-1854, San Diego, U.S.A, May 2012.
[3]Huang C., Wang B., Li T., and Wei H., “Analysis of Temperature Field of Embedded Multi-Chip Module,” Proceeding of the 12th ICEPT-HDP (International Conference on Electronic Packaging Technology & High Density Packaging), pp. 801-805, Shanghai, China, August 2011.
[4]LI, P., PAN, K. L. and Ning, Y. X., “Finite Element Analysis of Reliability on Compliant Wafer Level Packaging With Compliant Layer,” Proceeding of the 9th ICEPT-HDP (International Conference on Electronic Packaging Technology & High Density Packaging), pp. 1-4, Shanghai, China, July 2008.
[5]Zhang, Z., Deng, Y. L., Liu, Y. L. and Jin, Y. F., “Reliability Simulation of Metal Bump in a Three-Dimensional Chip Stacking Structure,” Proceeding of the 11th ICEPT-HDP (International Conference on Electronic Packaging Technology & High Density Packaging), pp. 1218-1220, Xi’an, China, Aug. 2010.
[6]Lu, C. L. and Yeh, M. K., “Thermal Cycling Analysis of Microgyroscope Chip Embedded with Through-Silicon Vias by Finite Element Method,” Proceeding of the 5th IMPACT (International Microsystems Packaging Assembly and Circuits Technology), pp. 1-4, Taipei, Taiwan, Oct. 2010.
[7]Cao, Y. S., Jiang, T., Liu, J. and Lian, B., “The Study for Thermal Analysis Technology of Three-Dimension SRAM Component,” Proceeding of the 8th ICEPT (International Conference on Electronic Packaging Technology), pp. 1-4, Shanghai, China, Aug. 2007.
[8]Wen, S. S. and Lu, G. Q., “Finite Element Modeling of Heat Transfer and Thermal Stresses for Three-dimensional Packaging of Power Electronics Modules,” Proceeding of the 3th IPEMC(International Power Electronics and Motion Control), pp. 496-501, vol. 1, Beijing, China, Aug. 2000.
[9]Yoon, S. W., Witarsa, D., Lim S. Y. L. and Ganesh V., “Reliability Studies of a Through Via Silicon Stacked Modulefor 3D Microsystem Packaging,” Proceeding of the 56th ECTC(Electronic Components and Technology Conference), pp.1-5, San Diego, CA, July 2006.
[10]Hsieh, M. C., Wu, S. T., Li, W., Tain, R. M., Lau, J. H., Lo, R. and Kao, M. J., “Nonlinear Thermal Stress Analyses and Design Guidelines for Through Silicon Vias (TSVs) in 3D IC Integration,” Proceeding of the 6th IMPACT(International Microsystems, Packaging, Assembly and Circuits Technology), pp.75-78, Taipei, Taiwan, October 2011.
[11]Gao, G. L., Haba1, B., Oganesian, V., Honer, K., Ovrutsky, D., Rosenstein C., Axelrod E., Hazanovich F. and Aksenton Y., “Compliant Wafer Level Package for Enhanced Reliability,” Proceeding of 6th. Int. Conf. on High Density packaging and Microsystem Integration, pp.1-5, 26-28 June 2007.
[12]Wu, Z. Y., Huang, Z. H., Conway, P. P. and Ma, Y. C., “Effect of Microstructure on Thermal-Mechanical Stress in 3D Copper TSV Structures,” Proceeding of the 13th EPTC (Electronics Packaging Technology Conference), pp. 450-454, Singapore, Dec. 2011.
[13]Kinoshita, T., Takashi, K., Takeshi,W., Shunpei, S., et al., “Actual stresses around TSV in whole 3D-SiP under reflow or power ON/OFF thermal load,” Proceeding of the 7th IMPACT (International Microsystems Packaging Assembly and Circuits Technology), pp. 243-246, Taipei, Taiwan, Oct. 2012.
[14]Xu, S. T. and Li, X. B., “Analysis on Thermal Reliability of Key Electronic Components on PCB Board,” Proceeding of the ICQR2MSE(Quality, Reliability, Risk, Maintenance, and Safety Engineering), pp. 52-54, Xi’an, China, June 2011.
[15]Hsieh, M. C. and Yu, C. K., “Thermo-mechanical Simulations For 4-Layer Stacked IC Packages,” Proceeding of 9th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2008, pp.1-7, April 2008.
[16]Tang, C. Y., Tsai, M. Y., Yen, C. Y. and Chang,L. B., “Characterization of Thermal and Optical Behaviors of Flip-Chip LED Packageswith Various Underfills,” Proceeding of the 6th IMPACT (International Microsystems Packaging Assembly and Circuits Technology), pp. 327-331, Taipei, Taiwan, Oct. 2011.
[17]Chen, R. S., Huang, C. H. and Huang, Z. X., “Optimal Design of Dissipation for the Array Power LED by the Genetic Algorithm,” Proceeding of the 7th IMPACT(International Microsystems, Packaging, Assembly and Circuits Technology), pp.219-222, Taipei, Taiwan, October 2012.
[18]Houl, F. G., Yang, D. G., Zhang, G. Q. and Liu, D. J., “Research on Heat Dissipation of High Heat Flux Multi-Chip GaN-Based White LED Lamp,” Proceeding of the 12th ICEPT-HDP (International Conference on Electronic Packaging Technology & High Density Packaging), pp.1101-1105, Guilin, China, Aug. 2011.
[19]Hou, F. Z., Yang, D. G., Zhang, G. Q., Hai, Y., Liu, D. J. and Liu, L., “Thermal Transient Analysis of LED Array System with In-line Pin Fin Heat Sink,” Proceeding of the 12th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), pp. 1-5,Guilin, China, April 2011.
[20]侯順雄,王松浩,張仲卿,熱傳遞,高立圖書有限公司,台北,第3-10頁,2007。
[21]Ozisik, M. N., Basic Heat Transfer, McGraw-Hill, Library of Congress Cataloging, the United States of America, pp.302-311, 1977.
[22]Lau, J. H., Thermal Stress and Strain in Microeletronics Packaging, VAN NOSTRAND REINHOLD, New York, pp.2-8,1993.
[23]Tsai, S. W., and Hahn, H. T., Introduction to Composite Materails, TECHNOMIC Publishing Co., Inc. 1980 265 Post Road West, Westport, pp. 379-394, 1985.
[24]Z公司提供。
[25]http://www.matweb.com/
[26]http://alasir.com/reference/solder_alloys/
[27]http://www.kayelaby.npl.co.uk/general_physics/2_3/2_3_6.html
[28]Lau, J. H., Low Cost Flip Chip Technologies: for DCA, WLSCP, and PBGA Assemblies, McGraw-Hill, pp.533, 2000.

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