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研究生:許庭瑜
研究生(外文):Ting-Yu Shyu
論文名稱:適用高能效微處理器之按需時序臆測設計分析
論文名稱(外文):Analysis of On-Demand Timing Speculation for Energy-Efficient Microprocessors
指導教授:林泰吉
指導教授(外文):Tay-Jyi Lin
口試委員:郭峻因葉經緯鍾菁哲林泰吉
口試委員(外文):Jiun-In GuoChingwei YehChing-Che ChungTay-Jyi Lin
口試日期:2013-07-31
學位類別:碩士
校院名稱:國立中正大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:51
中文關鍵詞:可變延遲時序臆測抗變異
外文關鍵詞:Variable latencyTiming speculationVariation tolerant
相關次數:
  • 被引用被引用:4
  • 點閱點閱:357
  • 評分評分:
  • 下載下載:26
  • 收藏至我的研究室書目清單書目收藏:0
先進製程在製程(process)、電壓(voltage)、溫度(temperature)以及資料(data patterns)上變異的狀況相當嚴重,在一般考慮最差狀況的設計下在效能將受到很大的影響,可變延遲路徑技術可以避免最差狀況的設計,可以針對一般狀況設計,進而提升效能,而Razor是一個使用電路層級時序臆測的可變延遲路徑技術,是一個有前景的技術,與一般的靜態的方法相比,它可以動態地容忍PVT的變異,但額外的時脈延遲、維持時間(hold time)的限制以及臆測機制多餘的開銷是Razor的問題所在,在本論文中,我們分析我們所提出的按需時序臆測(ODTS;on-demand timing speculation)以及Razor在能效上的差異,為了驗證我們的方法,也實作了加上ODTS方法的微處理器至FPGA。
PVTD (process, voltage, temperature and data patterns) variations effect strongly in advanced technology. Worst-case designs have pool performance under high variation environment. Variable latency design is to prevent worst-case design and increase the performance by designing for typical case. Razor is a variable latency design using circuit level timing speculation. It is a promising technology because it dynamically tolerant PVT variations compared with conventional static design approaches. But Razor has some problems: extra clock delay, hold time constraint and overheads of timing speculation. In this thesis, we analyze our proposed ODTS (on-demand timing speculation) and Razor by comparing their energy-efficiency. For verifying our method, we also implement a microprocessor using ODTS in FPGA.
誌 謝 i
中 文 摘 要 ii
Abstract iii
目錄 iv
圖目錄 v
表目錄 vi
第一章 序論 1
1.1 先進製程與延遲變異 1
1.2 研究動機與目的 4
1.3 論文架構 5
第二章 可變延遲路徑技術 6
2.1望遠鏡單元 7
2.2功能臆測 9
2.3 Razor設計 11
第三章 ODTS技術 14
3.1 基本概念 14
3.2 臆測與容錯機制 16
3.3 處理器設計之應用 19
第四章 設計實作及分析 26
4.1 資料路徑功效分析 26
4.2 臆測機率之效能差異 33
4.3 FPGA驗證 36
第五章 結論 40
參考文獻 41


[1]B. H. Calhoun and D. Brooks, “Can subthreshold and near-threshold circuits go mainstream?” IEEE Micro, Jul.-Aug., 2010
[2]A. P. Chandrakasan, et al., “Technologies for ultradynamic voltage scaling,” in Proc. IEEE, vol. 98, pp. 191-214, Feb. 2010
[3]L. Benini, E. Macii, and M. Poncino, "Telescopic units: increasing the average throughput pipelined designs by adaptive latency control," in Proc. DAC, pp.22-27, Jun. 1997
[4]L. Benini, E. Macii, M. Poncino, and G. De Micheli, “Telescopic units: a new paradigm for performance optimization of VLSI designs,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 17, pp.220-232, Mar. 1998
[5]Y. S. Su, D. C. Wang, S. C. Chang, and M. Marek-Sadowska, “An efficient mechanism for performance optimization of variable-latency designs,” in Proc. DAC, pp.976-981, 2007
[6]Y. S. Su, D. C. Wang, S. C. Chang, and M. Marek-Sadowska, "Performance optimization using variable-latency design style," IEEE TVLSI , vol.19, no.10, pp.1874-1883, Oct. 2011
[7]S. Gupta, S.S. Sapatnekar, "BTI-aware design using variable latency units," in Proc. ASP-DAC, pp.775-780, 2012
[8]D. Baneres, J. Cortadella, and M. Kishinevsky, "Variable-latency design by function speculation," in Proc. DATE., pp.1704-1709, 2009
[9]Y. Liu; Y. Sun; Y. Zhu; H. Yang, "Design methodology of variable latency adders with multistage function speculation," in Proc. ISQED, pp.824-830, 2010
[10]Verma, A.K.; Brisk, P.; Ienne, P., "Variable latency speculative addition: a new paradigm for arithmetic circuit design," in Proc. DATE, pp.1250-1255, 2008
[11]D. Ernst, et al., “Razor: a low-power pipeline based on circuit-level timing speculation,” in Proc. MICRO, 2003, pp.7-18
[12]S. Das, et al., “RazorII: in situ error detection and correction for PVT and SER tolerance, ” IEEE JSSC, vol.44, no.1, pp.32-48, Jan. 2009
[13]M. Fojtik, et al., "Bubble Razor: eliminating timing margins in an ARM Cortex-M3 processor in 45 nm CMOS using architecturally independent error detection and correction," IEEE JSSC, vol.48, no.1, pp.66-81, Jan. 2013
[14]T. J. Lin, Y. T. Kuo, Y. J. Tsai, T. Y. Shyu, and Y. H. Chu, “Energy-efficient RISC design with on-demand circuit-level timing speculation,” in Proc. ASP-DAC, Jan. 2012
[15]T. J. Lin, et al., “A 0.48V 0.57nJ/pixel video recording SoC in 65nm CMOS,” in Proc. ISSCC, Feb. 2013
[16]Cortex M0 Processor, ARM Ltd., [Online]. Available:http://www.arm.com/products/processors/cortex-m/cortex-m0.php
[17]M. Guthaus, et al., “MiBench: a free, commercially representative embedded benchmark suite”, in Proc. 4th IEEE Annual Workshop on Workload Characterization, pp.3-14, Dec. 2001
[18]ZedBoard, Available: http://www.zedboard.org/
[19]Zynq-7000 All Programmable SoC, Xilinx Ltd., [Online]. Available: http://www.xilinx.com/zynq

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