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研究生:蔡維晉
研究生(外文):Tsai, Wei-Chin
論文名稱:具訊號特性感知之低功率逐漸逼近式生醫類比數位轉換器
論文名稱(外文):Signal-Feature-Aware Low-Power SAR-ADC for Biomedical Applications
指導教授:王進賢
指導教授(外文):Wang, Jinn-Shyan
口試委員:王進賢吳添祥黃崇勛
口試委員(外文):Wang, Jinn-ShyanWu, Tian-XiangHuang, Chung-Hsun
口試日期:2012-07-27
學位類別:碩士
校院名稱:國立中正大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:75
中文關鍵詞:逐漸逼近式類比數位轉換器低功率
外文關鍵詞:SAR ADCLow Power
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本論文實現了一個具訊號特性感知之低功率逐漸逼近生醫類比數位轉換器,使用的製程是NTC 0.35μm 2P3M CMOS process。本論文逐漸逼近式演算法使用手動或自動偵測訊號類型選擇使用的演算法,演算法分為二分搜尋式與移動搜尋式,跟具訊號的快慢選擇適用的演算法,達到低功率的需求。本論文提出之具訊號特性感知之低功率逐漸逼近生醫類比數位轉換器,在取樣頻率為10kHz下,當輸入訊號為139Hz時,由模擬結果可以達到雜訊失真比為72.01dB、有效位元為11.6bit、總功率消耗為845μW。
This thesis presented a Signal-Feature-Aware Low-Power SAR-ADC for Biomedical Applications in NTC 0.35μm 2P3M CMOS process. This thesis presented a SAR algorithms use manually or automatically detect the signal type selection algorithm, the algorithm is divided into binary search algorithm and moving binary search algorithm, select the applicable algorithm based on the speed of the signal to achieve low power consumption. Simulation results show that the SNDR and ENOB of the SA-ADC with an input frequency of 139Hz under sampling frequency of 10kHz are 72.01dB and 11.6bit, total power consumption is 845μW.
摘要 iii
Abstract iv
誌謝辭 v
目錄 vi
圖目錄 ix
表目錄 xii
第一章 緒論 1
1.1 研究背景與動機 1
1.2 研究動機與目的 1
1.3 論文架構 3
第二章 類比數位轉換器架構與簡介 4
2.1 類比數位轉換器簡介 4
2.1.1 解析度 (Resolution) 4
2.1.2 輸入範圍 (Input Range) 5
2.1.3 訊號雜訊比 (Signal-To-Noise Ratio, SNR) 6
2.1.4 訊號雜訊失真比 (Signal-To-Noise+ Distortion Ratio, SNDR) 8
2.1.5 有效位元 (Effective Number of Bits, ENOB) 8
2.1.6 動態範圍 (Dynamic Range) 8
2.1.7 微分非線性誤差 (Differential Nonlinearity, DNL) 9
2.1.8 積分非線性誤差 (Integral Nonlinearity, INL) 10
2.1.9 位移誤差 (Offset) 10
2.1.10 增益誤差 (Gain Error) 11
2.2 類比數位轉換器架構 12
2.2.1 快取式類比數位轉換器 (Flash ADC) 13
2.2.1.1 Sparkles in Thermometer Code 15
2.2.1.2 Metastability in Flash ADC 15
2.2.2 摺疊內插式類比數位轉換器(Folding and Interpolation) 16
2.2.2.1 摺疊式類比數位轉換器(Folding ADC) 17
2.2.2.2 內插式類比數位轉換器(Interpolation ADC) 17
2.2.3 兩階段式類比數位轉換器 ( Two-Step ADC ) 19
2.2.4 管線式類比數位轉換器 ( Pipelined ADC ) 20
2.2.5 逐漸逼近式類比數位轉換器 (SAR ADC) 22
2.2.6 分時並行式類比數位轉換器 ( Time-Interleaved ADC ) 24
第三章 逐漸逼近式類比數位轉換器架構 26
3.1 逐漸逼近式類比數位轉換器簡介 26
3.2 取樣保持電路(S/H) 27
3.2.1 採樣 MOS 開關 27
3.2.2 取樣保持電路設計 31
3.2.3 取樣保持電路模擬結果 32
3.3 比較器電路 33
3.3.1 比較器電路設計 33
3.3.2 比較器電路模擬結果 34
3.4 數位類比轉換器(DAC) 35
3.4.1 電阻式數位類比轉換器 36
3.4.2 電流式數位類比轉換器 37
3.4.3 電容式數位類比轉換器 37
3.4.4 改良式電容式數位類比轉換器 38
3.4.5 數位類比轉換器電路模擬結果 40
3.5 逐漸逼近式暫存器(SAR) 43
3.5.1 逐漸逼近式暫存器電路設計 43
3.6具訊號特性感知逐漸逼近式暫存器 45
3.6.1 具訊號特性感知逐漸逼近式暫存器 45
3.6.2 移動搜尋演算法的運作模式 46
3.6.3 二元搜尋與移動搜尋演算法結合 51
3.6.4具訊號特性感知逐漸逼近式暫存器模擬結果 52
3.7 ADC 整體電路佈局圖 53
第四章 具訊號特性感知之SAR-ADC模擬 54
4.1 SAR-ADC模擬結果 54
4.2 ADC模擬結果與比較 56
4.3 量測方法 57
4.3.1 電源調節電路(Power Regulator Circuit) 59
第五章 結論與未來展望 60
5.1 結論 60
5.2 未來方向 60
參考文獻 61

[1] Behzad Razavi, “Principles of Data Conversion System Design,” IEEE Press, 1995.
[2] Bernhard E. Boser, EECS 247 Lecture, University of California at Berkeley.
[3] Behzad Razavi, “Design of analog CMOS integrated circuits,” McGraw-Hill Companies, Inc.2002
[4] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, May 1999.
[5] David A. Johns, Ken Martin, “Analog integrated circuit design”, John Wiley & Sons, Inc., 1997.
[6] S. Mortezapour, and E. K. F. Lee, “A 1-V, 8-bit successive approximation ADC in standard CMOS process,” IEEE Journal of Solid-State Circuits, vol. 35 Issue. 4, pp. 642-646, Apr 2000
[7] H. J. Schouwenaers, D. W. J. Greeneveld, and H. A. H. Tremeer, “A low-power stereo 16-bit CMOS D/A converter for Digital Audio,” IEEE Journal of Solid-State Circuits, vol. 23, no. 6, pp. 1290-1297, Dec 1988.
[8] P. E. Allen, D. R. Holberg “ CMOS Analog Circuit Design ”,Oxford,2002
[9] A. Agned, E. Bonizzoni, P. Malcovati, F.Maloberti, “A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with time domain comparator,” IEEE ISSCC 2008, SESSION 12, HIGH-EFFICIENCY DATA CONVERTERS 12.5
[10] Wen-Sin Liew, Libin Yao and Yong Lian, “A Moving Binary Search SAR-ADC for Low Power Biomedical Data Acquisition System,” Circuits and Systems, 2008. APCCAS . IEEE Asia Pacific Conference on, pp. 646 – 649, Nov. 30 2008-Dec. 3 2008
[11] Harald Neubauer, Thomas Dese, Hans Hauer, “A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 μm CMOS using self calibration and low power techniques,” Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
[12] Wen-Yi Pang, Chao-Shiun Wang, You-Kuang Chang, Nai-Kuan Chou, and Chorng-Kuang Wang, “A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical applications ,” IEEE Asian Solid-State Circuits Conference November 16-18, 2009 / Taipei, Taiwan
[14] Lungui Zhong, Haigang Yang, “Design of an Embedded CMOS CR SAR ADC for Low Power Applications in Bio-Sensor SOC,” ICASIC 2007 . pp. 668-671
[15] Sung-Min Chin and Chih-Cheng Hsieh, Chin-Fong Chiu and Hann-Huei Tsai “A New Rail-to-Rail Comparator with Adaptive Power Control for Low Power SAR ADCs in Biomedical Application,” ISCAS, May 30 2010-June 2, pp. 1575 - 1578
[16] Chou, P.H. ; Ying Bai ; Matthews, R. ; Hibbs, A. , “An Ultra-Wearable, Wireless, Low Power ECG Monitoring System,” Biomedical Circuits and Systems Conference, 2006. BioCAS 2006. IEEE, Nov. 29 2006-Dec. 1 2006, pp. 241-244
[17] Chao-Shiun Wang, Chorng-Kuang Wang, “A 8-bit 500-KS/s Low Power SAR ADC for Bio-Medical Applications,” Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian, 12-14 Nov. 2007, pp. 228-231
[18] YoungJae Min, Yonghwan Kim, Soowon Kim, “A Low Power Consumption 10 bit Rail to Rail SAR ADC Using a C-2C Capacitor Array,” Electron Devices and Solid-State Circuits, 2008. EDSSC 2008. IEEE International Conference on, 8-10 Dec. 2008, pp. 1-4
[19] Wen-Sin Liew, Libin Yao, Yong Lian, “A 1V 22μW 32-Channel Implantable EEG Recording IC,” Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 7-11 Feb. 2010, pp. 126-127
[20] 王進賢, “VLSI電路設計,” 2003, 高立, ISBN:957-584-819-5

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