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研究生:張倍耀
研究生(外文):Pei-Yao Chang
論文名稱:超低電壓之系統單晶片記憶體設計
論文名稱(外文):On Chip Memory Designs for Ultra-Low-Voltage SoC
指導教授:王進賢
指導教授(外文):Jinny-Shyan Wang
口試委員:吳重雨王進賢郭峻因陳添福黃錫瑜葉經緯林泰吉
口試委員(外文):Chung-Yu WuJinn-Shyan WangJiun-In GuoTien-Fu ChenShi-Yu HuangChingwei YehTay-jyi Lin
口試日期:2013-07-02
學位類別:博士
校院名稱:國立中正大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:122
中文關鍵詞:記憶體系統單晶片
外文關鍵詞:MemorySoC
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超低工作電壓之系統單晶片已變成近年的設計潮流,而低操作電壓也造成晶片上記憶體的各種設計困難。本論文提出互補式金屬氧化物半導體製程下,各種嶄新低電壓且具高效能的記憶體電路技術,包含了靜態隨機存取記憶體、資料暫存器、唯讀記憶體電路。
首先,為了可超寬動態電壓調整的多工處理器需求,我們提出一個4讀2寫的資料暫存器電路,其細胞元搭配全N型獨立讀取端,在次臨界電壓操作下達到節省功率消耗以及改善讀取效能,此外我們還提出一個可重構式的暫存器寫入電路,利用控制單工運算的方式,加強暫存器寫入電路之雜訊免疫力。上述技術透過65奈米製程驗證並下線,測試晶片可最低操作電壓為148mV。
第二,我們發表了一個應用於H.264影像解碼器之次臨界電壓嵌入式靜態隨機存取記憶體。在這個作品裡,除了應用傳統的7T記憶體細胞元,並搭配功率閘技術與多輸出動態解碼電路,其目的於可操作在更低的電壓與避免更多的電路面積消耗,以及在低電壓下具有更快的操作頻率。上述技術實現在8Kb容量下的記憶體電路,並已成功驗證於90奈米製程。
另外,本論文發表兩個低電壓具雜訊容忍功能的65奈米記憶體測試晶片。包含一個容量8Kb之靜態隨機存取記憶體與一個容量512Kb之影像緩衝器。其主要技術在處理製程上即時變異與資料相依性的問題,提出技術有資料位元預測電路搭配無致能感測放大器,以及動態轉態點感測放大器。
最後,本論文設計一個次臨界電壓操作之256Kb非或閘型唯讀記憶體,利用階層化資料位元線搭配交錯式陣列,以及漏電流追蹤N型守衛電路與半追蹤資料位元線感測技術。此非或閘型唯讀記憶體經90奈米製程下線,並驗證其最低操作電壓為0.22V。
本論文發表多種記憶體電路技術,透過各式廣泛分析與模擬,搭配各式製程下線,最後驗證並測試所有記憶體晶片,證明此技術可讓記憶體電路在系統單晶片中擁有更低操作電壓、更高工作效能與更加的穩定性。

Ultra-low voltage operations have become popular alternatives for SoCs design in recent years. However, at a lower supply voltage, on-chip nanometer memories suffer from many problems. This dissertation gives comprehensive descriptions of several low-voltage and energy-efficient techniques of the memory circuit, and proposes several low-voltage memory circuits including the COMS process of the Static Random Access Memory (SRAM), Register File (RF), and Read Only Memory (ROM).
First, a 4R/2W register file design for 2-issue microprocessors with ultra-wide dynamic voltage scaling is presented. A full-N separated read port has been proposed to save the area and to improve the performance for subthreshold operations. In addition, a reconfigurable write scheme has been proposed to utilize the unused write port with single-issue execution for the WNM improvement. A test chip has been designed and fabricated using 65nm process, of which a minimum operating voltage of 148mV has been measured. Second, the design of embedded subthreshold SRAMs for a quality-scalable H.264 video decoder IP is presented. In addition to the conventional 7T SRAM bitcell, power-gating techniques and multi-output dynamic circuits were adopted in order to achieve a low VDDmin, a small area overhead, and a higher operating speed. A 8Kb 90-nm SRAM macro has been designed for verifying the proposed techniques. Third, the low-voltage and variation-tolerant SRAMs are implemented in two 65nm test chips, including a 8Kb SRAM macro (0.25-1.0V) and a 512Kb frame buffer (0.45-1.0V). The main design techniques include a bitline leakage prediction scheme with a non-trimmed non-strobed S.A. or dynamic trip point S.A. to deal with process and runtime variations and data dependence. Finally, a 256Kb NOR-ROM is a design that realizes the proposed hierarchical bitline scheme with interleaved shielding and leakage-tracking NMOS keepers with half-rate-bit-line tracking sensing. The NOR-ROM has been fabricated in 90nm CMOS, of which the measured VDDmin is 0.22V.
Several experimental chips of the proposed circuits are designed and fabricated. Through extensive analyses, simulations, fabrications and measurements, all proposed techniques for memory are verified. Memory circuits proposed in this dissertation allow lower supply voltage and more energy-efficient and more reliability in SoCs.

Chapter 1 Introduction 1
1.1 BACKGROUND OF LOW-VOLTAGE SYSTEM ON CHIP 1
1.2 MOTIVATION 5
1.3 DISSERTATION ORGANIZATION 7
Chapter 2 Study of the Traditional Low- Voltage Memory Design 9
2.1 TRADITIONAL MEMORY STRUCTURE 10
2.2 LOW-VOLTAGE EMBEDDED SRAM CIRCUIT 11
2.2.1 Read/Write Assist Peripheral Circuit 12
2.2.2 SRAM Cell Structure 14
2.2.3 Sense Amplifier Circuit Design 19
2.3 EMBEDDED REGISTER FILES CIRCUIT 22
2.3.1 Register Files Structure 22
2.3.2 Local Bit Line Circuit 24
2.4 EMBEDDED ROM CIRCUIT 27
2.4.1 NAND-type ROM Structure and Operation 27
2.4.2 NOR-type ROM Structure and Operation 28
2.4.3 Comparison of NAND-type and NOR-type ROM 30
2.5 SUMMARY 31
Chapter 3 The Ultra Low-Voltage /Energy-Efficient 4R/2W Regfiles 32
3.1 INTRODUCTION 32
3.2 PROPOSED 4R/2W REGFILE DESIGN 34
3.2.1 Regfile Structure 35
3.2.2 Full-N Read Port Scheme 36
3.2.3 Reconfiguable Write Scheme 37
3.3 CIRCUIT COMPARISON 40
3.4 EXPERIMENTAL RESULTS 43
3.5 SUMMARY 45
Chapter 4 The Low-Voltage/Low-Cost/Quality-Scalable SRAM 46
4.1 INTRODUCTION 46
4.2 DESIGN CHALLENGES OF THE QUALITY-SCALABLE VIDEO DECODER 48
4.3 ANALYSIS OF CONVENTIONAL 7T SRAM 50
4.4 PROPOSED A7T SRAM 54
4.4.1 The a7T Bit Cell 55
4.4.2 GND Gating 56
4.4.3 VDD Gating 60
4.4.4 Address Decoder 61
4.5 SIMULATION AND EXPERIMENTAL RESULTS 63
4.5.1 Effectiveness of the reduction of the VDDmin 63
4.5.2 Monte Carlo simulations 64
4.5.3 Experimental Results 65
4.6 SUMMARY 68
Chapter 5 The Sub-Threshold and Variation-Tolerant SRAM 69
5.1 INTRODUCTION 69
5.2 DESIGN CHALLENGE OF THE LEAKAGE PROBLEMS 70
5.3 PROPOSED LEAK-AWARE SRAM DESIGN 71
5.3.1 Bitline Leakage Prediction 71
5.3.2 Non-trimmed Non-strobed Sense Amplifier 73
5.3.3 Dynamic Trip Point Sense Amplifier 76
5.4 EXPERIMENTAL RESULTS 78
5.5 SUMMARY 83
Chapter 6 Ultra Low-Voltage/ Energy-Efficient ROM 84
6.1 INTRODUCTION 84
6.2 DESIGN CHALLENGE OF THE LOW-VOLTAGE ROMS 85
6.2.1 Problems with the Conventional ROMs 85
6.2.2 ULV ROM Designs 89
6.3 THE PROPOSED HBIS NOR-ROM 91
6.4 CHIP DESIGN & SILICON IMPLEMENTATION 97
6.4.1 The leakage-tracking NMOS (LTN) keepers 97
6.4.2 HRBLT Sense Amplifier 99
6.4.3 Effectiveness of the reduction of the power 100
6.5 EXPERIMENTAL RESULTS 102
6.6 SUMMARY 105
Chapter 7 Conclusions and Future Works 106
7.1 CONCLUSIONS 106
7.2 FUTURE WORKS 111
Bibliography 115

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