( 您好!臺灣時間:2021/07/24 03:33
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::


研究生(外文):Zhang, Zhanwei
論文名稱(外文):A Numerical Analysis of the Flexural Strength of Thin TSV Wafer Die
指導教授(外文):Liu, D. S.
口試委員(外文):Chen, C. I.Hsu, HsiangchenLin, Paichen
外文關鍵詞:Through Silicon ViaPlate ElementInfinite Element AnalysisFinite Element Analysis
  • 被引用被引用:0
  • 點閱點閱:582
  • 評分評分:
  • 下載下載:20
  • 收藏至我的研究室書目清單書目收藏:0
近年來晶片趨向輕薄短小、低耗電、低成本與多功能的需求,故晶片在系統中可使用的空間愈來愈小,因此發展三維矽穿孔(Through Silicon Via; TSV)多晶片堆疊封裝(Stacked-Die Packaging; SDP)技術是極重要的封裝發展方向。當晶片數量增加時,必須經由減少晶片厚度來達到既有晶片堆疊的空間,而多晶片封裝若有一顆IC失效,將連帶造成整個IC無法運作,故在封裝第一階段,需應用超薄TSV晶圓之針測技術(Thin TSV Wafer Probing Techniques),即時檢測出不良晶粒。本研究將應用四點彎矩(Four-Point Bending,4PB)模擬超薄TSV晶圓針測時所產生之晶圓強度,此外本研究建立薄板元素(Plate Element)之無限元素(Infinite element)的計算方法,並利用此分析模型結合有限元素法探討不同孔徑大小、厚度對薄晶圓強度之影響。
Light weight, small size, low voltage, and low cost are the mainly request of high performance IC product; on the other hand, it also means the spacing for IC system is very limited. Therefore to develop the Through Silicon Via (TSV) Stacked-Die Packaging (SDP) is the current important direction for advance packaging technique. TSV/SDP need to support with thin wafer so that the stacking dies could maintain the spacing limitation, however any failure die could lead to lower the yield rate and increasing the manufacturing cost. Therefore, a highly needed technique at the first phase of the package is to develop of ultra-thin TSV Wafer Probing Techniques for better detecting of failure dies and improve the yield rate of SDP. In this study we applied four-point bending to analyze the die strength of probing ultra-thin TSV Wafer. We also developed an analytical method, using plate element sets up infinite element Analysis (IEA) model combined with the Finite Analysis(FEA) model to analyze the size and thickness effect of TSV.
表目錄 VII
圖目錄 IX
第一章 緒論 1
1-1 研究動機 1
1-2 研究目的 4
1-3 文獻回顧 5
1-3-1 彎矩試驗對晶圓強度的探討 5
1-3-2 晶圓受熱負載之應力分佈探討 9
1-3-3 文獻回顧總結 15
1-4 研究方法、進行步驟與流程 16
1-4-1 3D與2.5D模擬 17
1-4-2 無限元素法 19
第二章 無限元素法介紹 21
2-1 薄板無限元素法相似形狀元素剛性矩陣之關係 21
2-2 薄板無限元素法之剛性矩陣計算 26
2-3 薄板無限元素法之不同層數剛性矩陣運算推導 29
2-4 薄板無限元素法之每一層位移運算推導 33
第三章 薄晶圓強度測試 35
3-1 薄晶圓強度實驗 35
3-2 3D有限元素模擬 37
3-2-1 邊界設定與材料性質給定 38
3-2-2 3D有限元素模型 38
3-3 2.5D有限元素模擬 39
3-3-1 邊界設定與材料性質給定 39
3-3-2 2.5D有限元素模型 39
3-4 結果與討論 40
第四章 無限元素法分析驗證 43
4-1 薄板無限元素法之範例驗證 43
4-2 無限元素法模擬結果 45
第五章 超薄TSV晶圓強度分析 49
5-1 晶圓之彎矩強度測試 49
5-2 超薄TSV晶圓之模擬尺寸與彎矩值 54
5-3 異質性無限元素法與ABAQUS之驗證 58
5-4 超薄TSV晶圓於不同尺寸下抗彎矩表現 61
第六章 結論與未來研究方向 65
6-1 結果與討論 65
6-2 未來研究發展 66
參考文獻 67

[1] Yole Development, http://www.yole.fr/, 2007
[2] http://www.samsung.com/global/business/semiconductor/support/ PackageInformation/pkg_technicalinfo_tsv. html
[3] ASTM, “Standard Test Methods for Flexural Properties of Unreinforced and Reinforced Plastics and Electrical Insulating Materials, ” D790-03
[4] ASTM, “Standard Test Method for biaxial flexure strength (modulus of rupture) of ceramic substrates substrates, ” ; ASTM F394-78. American Society for Testing and Materials, Philadelphia, PA. 1996
[5] Chae, S.H. ,and Zhao, J.H., “Effect of Dicing Technique on the Fracture Strength of Si Dies With Emphasis on Multimodal Failure Distribution, ” IEEE Transactions on Device and Materials Rellability vol. 10, no. 1, march , 2010.
[6] Lee, W.E., Lim, B.K. ,and Low, T.H., “Mechanical Characterization in Failure Strength of Silicon Dice, ”Packaging Analysis & Design Center United Test & Assembly Center Ltd (UTAC), 2004
[7] Stephan, S., Matthias, E., Christof, L., Karlheinz, B. ,and Jorg, B., “Investigations of The Influence of Dicing Techniques on The Strength Properties of Thin Silicon, ” Fraunhofer-Institute for Mechanics of Materials, 2007
[8] Alexander Polyakov, Timon Grob ,and Ron A. Hovenkamp, “Comparison of via-fabrication techniques for through-wafer electrical interconnect application ”, Electronic Components and Technology Conference, Proceedings, 54th , Vol. 2, Pages 1466-1470, 2004
[9] ASTM, “Standard Test Method for Monotonic Equibiaxial Flexural Strength of Advanced Ceramics at Ambient Temperature , ”C1499-03
[10] ASTM, “Standard Test Method for Flexural Properties of Unreinforced and Reinforced Plastics and Electrical Insulating Materials by Four-Point Bending, ”D6272-10
[11] K. Takahashi, Y. T.guchi, M. Tomisaka, H. Yonemura, M. Hoshino, M. Ueno, Y. Egawa, Y. Yamaji, H. Terao, M. Umemoto, K. Kameyama, A. Suzuki, Y. Okayama, T. Yonezawa, and K. Kondo, “Process Integration of 3D Chip Stack with Vertical Interconnection,” IEEE Electronic Components and Technology Conference, Vol. 1, pp. 601-609, Las Vegas, NV, USA, June 1-4, 2004
[12] SEMI, “Test Method for Measurement of Chip (Die) Strength by Mean of 3-Point Bending, ”G86-0303
[13] C. J. Wu, M. C. Hsieh, K. N. Chiang, “Strength evaluation of silicon die for 3D chip stacking package using ABF as dielectric and barrier layer in through-silicon via”, Microelectronic Engineering, Vol. 87, Issue 3, Pages 505-509, 2010
[14] Y. Yang, R. Labie, F. Ling ,and C. Zhao, “Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures”, Microelectronic Reliability, In Press, Corrected Proof, Available online, 2010
[15] Naotaka Tanaka ,and Tomotoshi Sato, “Mechanical effect of copper through-vias in a 3D die-stacked module”, Electronic Components and Technology Conference, Proceedings, 52nd, Pages 473-479, 2002
[16] Cheryl S. Selvanayagam, John H. Lau, et. al,“Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and their Flip-Chip Microbumps”, 2008 Electronic Components and Technology Conference, 2008
[17] K. H. Lu, P. S. Ho, et. al,“Thermo-Mechanical Analysis of Through Silicon Vias in 3-D Integration”, 2008
[18] X. Liu, Q. Chen, et. al,“Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV)”, 2009 Electronic Components and Technology Conference, 2009
[19] H. Kitada, N. Maeda, et. al,“Effects of Thinned Multi-Stacked Wafer Thickness on Stress Distribution in theWafer-on-a-Wafer (WOW) Structure”, 2009 Mater. Res. Soc. Symp. Proc. Vol. 1156, 2009
[20] X. P. Wang, and W. Y Yin,“Multi-Physics Characterization of Through Silicon Vias (TSV) in the Presence of a Periodic EMP”, Electrical Design of Advanced Packaging & Systems Symposium, IEEE , 2009
[21] C. McDonough, R. Geer, and W. Wang,“TSV Stress Testing and Modeling for 3D IC Applications”, IEEE Proceedings of 16th IPFA - 2009, China, 2009
[22] A. Klumpp ,and K. R. Merkel, “Through Silicon Via Technology and SLID-Assembly for Integrated Systems”, 11th international Workshop on Stress-Induced Phenomena in Metallization,2010
[23] Paul Ho,“Thermomechanical Reliability Challenges for 3D Interconnects” ,Microelectronics Reliability,2010
[24] Y.C. Tan, C.M. Tan, et al, “Electromigration performance of Through Silicon Via (TSV) – A modeling approach”, Microelectronics Reliability, 2010
[25] A.P. Karmarkar, and X. Xu, et al, “Material, Process and Geometry Effects on Through-Silicon Via Reliability and Isolation”, Mater. Res. Soc. Symp. Proc. Vol. 1249, 2010
[26]. M. Hsieh, C. Yu, and S. Wu, “Thermo-Mechanical Simulative Study for 3D Vertical Stacked IC Packages with Spacer Structures”, 26th IEEE SEMI-THERM Symposium, 2010
[27] H. C. Cheng, and C. T. Lin,et.al, “A Clamped Through Silicon Via (TSV) Interconnection for Stacked Chip Bonding Using Metal Cap on Pad and Metal Column Forming in Via”, 2008 Electronic Components and Technology Conference, 2008
[28] J. Mitra, et al., “A Fast Simulation Framework for Full-Chip Thermo-Mechanical Stress and Reliability Analysis of Through-Silicon-Via based 3D ICs,” in IEEE Electronic Components and Technology Conf., 2011
[29] Kuan H. Lu et al., “Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias”, Proc 59th Electronic Components and Technology Conf, San Diego CA 2009, pp 630 – 634
[30] Xuefeng Zhang, “Chip package interaction(CPI) and its impact on the reliability of flip-chip packages’’,The University of Texas at Austin, 2009
[31] 蔡字原,2011,「超薄晶圓於BOR 測試中挫曲行為研究」,國立中正大學機械工程研究所碩士論文。
[32] 徐祥進,2010,「三點彎矩實驗之超薄晶圓強度分析與溫控針測實驗」,國立中正大學機械工程研究所碩士論文。
[33] Lem Tien Heng, “40μm Die Strength Characterization”, 10th Electronics Packaging Technology Conference ,Pages 328 - 337, 2008

第一頁 上一頁 下一頁 最後一頁 top