臺灣博碩士論文加值系統

本論文係研製一個“1.8~10.8-GHz UWB前端電路研製＂，將其接收端整合在一個晶片上，易於整合基頻電路，進而實現單系統晶片(SoC System on a Chip)的製作。在接收機的規劃上，對於室內無線應用發展之需求，著重於低功率消耗之特點並將射頻信號應用於1.8~10.8-GHz，以提高傳輸速度或降低傳輸能量。本論文包含：低雜訊放大器(LNA)、混頻器(mixer)與壓控振盪器(VCO)。系統規劃上，操作頻率為1.8~10.8-GHz，工作電壓為1.1V，基頻頻率為100-MHz。
在本論文中，所設計的低雜訊放大器增益為9.5dB、雜訊指數為3.1dB、輸入與輸出反射損耗均低於-10dB、功率消耗為21.1mW(含主動式巴倫)。降頻混頻器轉換增益為10.2dB、雙旁波帶雜訊指數為14.7dB、RF端反射損耗低於-10dB、功率消耗為17.5mW(含buffer)。壓控振盪器操作頻率為60GHz，輸出功率為-26.2dBm，相位雜訊為-98dBc/Hz@1MHz offset、可調頻率範圍58~60.02GHz。射頻前端電路，其轉換增益19.7dB、雜訊指數經計算為6.3~7.8dB、IIP3為-9.5dBm、總功率消耗38.6mW。電路採用Advanced Design System (ADS)軟體模擬以及TSMC 180nm 1P6M CMOS製程來完成。

This thesis presents the development of implementation of 1.8~10.8-GHz UWB front-end Circuits. The study is to integrate the transceiver circuit into a single chip to benefit the integration of the base-band circuit and to realize the manufacture of SoC (System on a Chip). For the demands of indoor wireless applications, the CMOS RF receiver is focused on low power consumption, and operated at 1.8~10.8-GHz to increase transmission rate. This paper includes low noise amplifier, down conversion mixer, and voltage-controlled oscillator. Planning the arrangement of the system, the RF operating frequency is from 1.8 to 10.8-GHz, and the supply voltage is 1.1V. The base band frequency is 100MHz.
In this thesis, low noise amplifier has a gain of 9.5dB and noise figure is smaller than 3.1dB. Both input and output return losses are smaller than those of -10dB. Power consumption is 21.1mW (w/i buffer). Down conversion mixer has a conversion gain of 10.2dB and double-sideband noise figure is smaller than 14.7dB. Return loss of RF Port is smaller than -10dB. Power consumption is 17.5mW (w/i buffer). The VCO output frequency of 60GHz, and output power of -26.2dBm, phase noise performance of -98dBc/Hz, and tuning range of 58~60.02GHz are obtained. The RF front-end simulated performance of the topology shows conversion gain of 19.7dBm, noise figure of 6.3~7.8dB, and IIP3 of -9.5dBm. The total power consumption is 38.6mW. The circuits are simulated and fabricated by Advanced Design System (ADS) and TSMC of 180 nm 1P6M CMOS process, respectively.

目 錄
指指導教授推薦書
口試委員審定書
長庚大學博碩士論文著作授權書............................iii
誌 謝....................................................iv
摘 要.....................................................v
Abstract.................................................vi
目 錄...................................................vii
圖 目 錄..................................................x
表 目 錄...............................................xiii
第一章 緒論...............................................1
1.1背景...............................................1
1.2研究動機...........................................1
1.3研究目的...........................................2
1.4論文架構...........................................2
第二章 射頻接收器系統架構分析.............................6
2.1簡介...............................................6
2.2超外差接收器.......................................6
2.3直接降頻接收器.....................................9
2.4雙降頻式接收器....................................13
2.5寬中頻與低中頻接收器..............................14
2.6接收器效能參數....................................17
2.6.1 雜訊指數....................................17
2.6.2 交互調變失真................................20
2.6.3 P1dB增益壓縮點..............................22
2.6.4穩定度.......................................23
第三章 超寬頻低雜訊放大器設計............................24
3.1簡介..............................................24
3.2超寬頻低雜訊放大器比較............................24
3.2.1回授式放大器.................................24
3.2.2分佈式放大器.................................25
3.3分佈式放大器雜訊模型推導..........................29
3.4匹配網路與增益....................................33
3.5 1.8~10.8-GHz低雜訊放大器設計.....................34
3.6 1.8~10.8-GHz CMOS低雜訊放大器之模擬結果...........35
第四章 超寬頻降頻混頻器..................................43
4.1簡介..............................................43
4.2降頻混頻器種類....................................44
4.2.1 單端型......................................44
4.2.2 單平衡型....................................45
4.2.3 雙平衡型....................................47
4.3降頻混頻器效能參數................................48
4.3.1 轉換增益...................................48
4.3.2 雜訊指數...................................49
4.3.3 隔離度.....................................50
4.3.4 P1dB 增益壓縮點與三階交互調變失真..........50
4.4 1.8~10.8-GHz 雙平衡降頻混頻器.....................51
4.5 1.8~10.8-GHz 低雜訊放大器與雙平衡降頻混頻器合併之模
擬結果...........................................54
第五章CMOS壓控振盪器....................................63
5.1振盪器簡介........................................63
5.2振盪器之基本原理..................................63
5.2.1 並聯回授....................................64
5.2.2 串聯回授…..................................66
5.3相位雜訊..........................................70
5.4相位雜訊對通訊系統的影響..........................71
5.5 L-C Tank振盪器原理...............................73
5.6壓控振盪器研究動機與目的..........................75
5.7壓控振盪器架構介紹................................76
5.8 CMOS壓控振盪器...................................78
5.8.1 電路架構....................................78
5.8.2 CMOS 壓控振盪器模擬結果.....................80
第六章 結論與未來展望....................................85
6.1結論..............................................85
6.2未來展望..........................................86
參考文獻.................................................87
圖 目 錄
圖1.1 射頻前端收發器.....................................3
圖1.2 設計流程...........................................4
圖1.3 系統規劃...........................................5
圖2.1 超外差接收器.......................................7
圖2.2 鏡像干擾...........................................8
圖2.3 (a)高中頻時中頻帶的干擾(b) 低中頻時中頻帶的干擾....9
圖2.4 直接降頻接收器架構簡圖............................10
圖2.5 自我混頻現象......................................11
圖2.6 二階諧波失真......................................12
圖2.7 增益與相位誤差....................................12
圖2.8 增益與相位誤差所造成的星座圖......................13
圖2.9 雙降頻式接收器架構方塊圖..........................14
圖2.10 寬中頻雙轉換接收器架構圖..........................15
圖2.11 低中頻雙轉換接收器架構簡圖........................16
圖2.12 單級電路雜訊指數..................................17
圖2.13 多級系統雜訊指數..................................18
圖2.14 非線性系統中的交互調變示意圖......................21
圖2.15 三階截斷點示意圖..................................22
圖2.16 Two-tone test.....................................22
圖2.17 P-1dB壓縮點......................................23
圖3.1 回授式放大器基本架構：(a) 基本串/並聯回授 (b) 局部回
授 (c)總體回授...................................25
圖3.2 分佈式放大器的基礎架構.............................27
圖3.3 MOS通道熱雜訊模擬................................29
圖3.4 MOS之分佈閘極電阻................................30
圖3.5 指叉式佈局........................................30
圖3.6 MOS電晶體之橫切面................................30
圖3.7 感應閘極等效雜訊電流源............................30
圖3.8 輸入極電晶體M1之雜訊模組.........................31
圖3.9 完整電路圖........................................35
圖3.10 1.8~10.8-GHz CMOS 低雜訊放大器之模擬..............38
圖3.11 1.8~10.8 GHz CMOS 低雜訊放大器之佈局圖.............42
圖4.1 單端MOSFET混頻器.................................45
圖4.2 單平衡MOSFET混頻器...............................46
圖4.3 雙平衡MOSFET混頻器...............................48
圖4.4 1.8~10.8-GHz CMOS雙平衡混頻器....................52
圖4.5 IF功率...........................................53
圖4.6 1.8~10.8-GHz 低雜訊放大器與雙平衡降頻混頻器模擬結
果...............................................57
圖4.7 1.8~10.8-GHz 低雜訊放大器與雙平衡混頻器合併之佈局
圖...............................................62
圖5.1 回授系統模型.....................................64
圖5.2 加上頻率選擇電路的回授振盪系統...................65
圖5.3 單端負阻振盪器等效電路...........................66
圖5.4 單端並聯模型負電阻振盪器等效電路.................68
圖5.5 兩埠負電阻振盪器示意圖...........................69
圖5.6 訊號偏移.........................................70
圖5.7 (a)理想振盪器之輸出頻譜 (b)實際振盪器之輸出頻譜..71
圖5.8 理想振盪器之降頻示意圖...........................72
圖5.9 實際振盪器之降頻示意圖...........................72
圖5.10 Negative-Gm Oscillator 示意圖......................73
圖5.11 CMOS L-C tank VCO................................74
圖5.12 主動埠產生之負電阻...............................75
圖5.13 無須申請各國通訊執照之60-GHz頻帶................75
圖5.14 CMOS LC-tank VCO常用的主動埠架構(a)NMOS交連耦合
對 (b)PMOS交連耦合對 (c)互補式交連耦合對.........77
圖5.15 變電容陣列單元..................................78
圖5.16 CMOS壓控振盪器電路架構.........................79
圖5.17 CMOS壓控振盪器之模擬...........................82
圖5.18 CMOS壓控振盪器電路佈局圖 .......................84
表 目 錄
表1.1 1.8~10.8-GHz 射頻前端接收器之系統規格表.............5
表3.1 1.8~10.8-GHz CMOS低雜訊放大器之模擬預計規格表......38
表3.2 Corner case在FF與SS之Post-simulation表現.........39
表3.3 工作電壓變動10%之Post-simulation表現..............40
表3.4 環境溫度變動至80°與0°之Post-simulation表現........41
表3.5 相關文獻比較表.....................................42
表4.1 Pre-simulation與Post-simulation之比較表...........58
表4.2 Corner case在FF與SS之Post-simulation表現.........59
表4.3 工作電壓變動10%之Post-simulation表現..............60
表4.4 環境溫度變動至-40°與80°之Post-simulation表現......61
表4.5 相關論文之比較.....................................62
表5.1 Pre-simulation與Post-simulation之比較表...........82
表5.2 Corner case在FF與SS之Post-simulation表現.........82
表5.3 工作電壓變動10%之Post-simulation表現..............82
表5.4 環境溫度變動至-40°與80°之Post-simulation表現......83
表5.5 相關論文之比較.....................................83

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