|
[1] S. Jin, J. Cho, X. D. Pham, K. M. Lee, S.-K. Park, M. Kim, and J. W. Jeon &;quot;FPGA Design and Implementation of a Real-Time Stereo Vision System, &;quot;IEEE Trans. Circuits and Systems for Video Technology, vol. 20, no. 1, Jan. 2010. [2] Takaya, K. and Zheng Qian, &;quot;FPGA Based Stereo Vision System to Display Disparity Map in Realtime,&;quot; 2012 International Conf. Information Science and Applications (ICISA), pp.1-4, May. 2012. [3] Ohmura. I, Mitamura. T, Takauji. H, and Kaneko. S, &;quot;A Real-time Stereo Vision Sensor based on FPGA realization of Orientation Code Matching,&;quot; 2010 International Symposium on Optomechatronic Technologies (ISOT), pp.1-5, Oct. 2010. [4] Wade S. Fife and James K. Archibald, &;quot;Improved Census Transforms for Resource-Optimized Stereo Vision, &;quot;IEEE Trans. Circuits and Systems for Video Technology, vol. 23, pp. 60-73, Jan. 2013. [5] Embedded System Design Using FPGAs,March 2013,URL: http://www.smdp.iitkgp.ernet.in/PDF%5CVLSI_DSP%5CEmbedded_System _Design.pdf [6] L. Nalpantidis, G. C. Sirakoulis, and A. Gasteratos, “Review of stereo vision algorithms: from software to hardware,” International Journal of Optomechatronics, vol. 2, no. 4, pp. 435-462, Nov. 2008. [7] John A. Kalomiros, John N. Lygouras, “Comparative Study of Local SAD and Dynamic Programming for Stereo Processing Using Dedicated Hardware,” EURASIP Journal on Advances in Signal Processing 2009. [8] R. Zabih and J. Woodfill, “Non-Parametric Local Transforms for ComputingVisual Correspondence,” Proc. Third European Conf. Computer Vision, pp. 150-158, 1994. [9] C. Zinner, M. Humenberger, K. Ambrosch, and W. Kubinger, “An optimized software-based implementation of a census-based stereo matching algorithm,” in Proceedings of the 4th International Symposium on Advances in Visual Computing, ser. ISVC ’08. Berlin, pp. 216-227, 2008. [10] 謝易錚,「以立體視覺實作盲人輔具系統」,國立中央大學資訊工程研究所 碩士論文,民國九十五年七月。 [11] Altera’s manual:Developing Peripheral for SOPC Builder,March 2013,URL:http://www.altera.com/literature/an/an333.pdf [12] Altera’s manual:Using SOPC Builder &; DSP Builder Tool Flow,March 2013,URL:http://www.altera.com/literature/an/an394.pdf [13] Altera’s manual:Nios II Embedded Peripherals IP User Guide,March 2013, URL:http://www.altera.com/literature/ug/ug_embedded_ip.pdf [14] Altera’s manual:Avalon Bus Specification Reference Manual,March 2013, URL:http://www.altera.com.cn/literature/manual/mnl_avalon_bus.pdf [15] Altera’s manual:Nios II Custom Instruction User Guide,March 2013,URL:http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdf [16] Altera’s manual:Creating Multiprocessor Nios II Systems tutorial,March 2013,URL: http://www.altera.com/literature/tt/tt_nios2_multiprocessor_tutorial.pdf [17] Altera’s manual:SOPC Builder Design Optimizations,March 2013,URL: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf [18] Altera’s manual:Hardware Acceleration and Coprocessing,March 2013, URL:http://www.altera.com/literature/hb/nios2/edh_ed51006.pdf [19] Altera’s manual:Memory System Design,March 2013,URL: http://www.altera.com/literature/hb/nios2/edh_ed51008.pdf [20] Altera’s manual:Nios II Core Implementation Details,March 2013,URL: http://www.altera.com/literature/hb/nios2/n2cpu_nii51015.pdf [21] Altera’s manual:Floating-Point Megafunctions User Guide,March 2013,URL: http:// www.altera.com/literature/ug/ug_altfp_mfug.pdf
|