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研究生:曹繼之
研究生(外文):Chi-Chih Tsao
論文名稱:奈米晶粒嵌入金屬氧化物對電阻式記憶體特性的影響
論文名稱(外文):Effects of nanocrystal embedded metal oxide on the switching characteristics in Resistive RAM
指導教授:康宗貴康宗貴引用關係
口試委員:吳文發林成利
口試日期:2013-06-28
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:65
中文關鍵詞:記憶體奈米晶粒奈米線局部電場良率
外文關鍵詞:MemoryNanocrystalNanowireLocal electrical fieldYield
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摘要 非揮發性記憶體在很多電子產品中是不可或缺的元件,近年來,文獻顯示,奈米晶粒嵌入介電層的電阻式記憶體有助提升金屬/介電層/金屬記憶體的特性與均勻性;另外,文獻也指出,奈米晶粒嵌入介電層,充當儲存層,得到不錯的金屬/阻絕層/奈米晶粒層/穿隧層/矽結構的記憶特性。本論文中的記憶體結構有兩部分,第一、將奈米晶粒嵌入介電層中不同的位置之電容結構。奈米晶粒嵌入的電容結構包括Pd/HfO2 (100Å)/TiN、Pd/HfO2 (75Å)/Pd NCs(7Å)/HfO2 (25Å)/TiN、Pd/HfO2(50Å)/Pd NCs(7Å)/HfO2(50Å)/TiN、Pd/HfO2(25Å)/Pd NCs(7Å)/HfO2 (75Å)/TiN,論文中探討了奈米晶粒不同位置的電容結構之良率、切換特性與耐久性,也提出一個奈米晶粒引發局部電場的機制來解釋量測到的數據。第二、奈米線結構氮化鈦奈米晶粒嵌入高介電材料非揮發性記憶體,此記憶體以氮化鈦奈米晶粒為儲存層。側壁空間層奈米線記憶體結構中,透過模擬發現奈米線的尖端有較高的電場,與平面記憶體結構比較,我們發現奈米線的尖端的局部電場可以增加寫入與抹除的速度並改善記憶視窗。


關鍵詞:記憶體、奈米晶粒、奈米線、局部電場、良率。
ABSTRACT In electronic products, the nonvolatile memory is an indispensable device. Recently, some research indicated that the resistive memory with nanocrystals embedded insulator showed better characteristics and switching uniformity. In addition, some research also showed that the nanaocrystals embedded the insulator serving as a storage layer, which obtained good memory characteristics in metal/blocking layer/ storage layer/tunneling layer/Si structure. In this thesis, there are two memory structures. Firstly, the metal/insulator/metal capacitors with Pd nanaocrystals located at different position. They include Pd/HfO2 (100Å)/TiN、Pd/HfO2(75Å)/Pd NCs(7Å)/HfO2(25Å)/TiN、Pd/HfO2 (50Å)/Pd NCs(7Å)/HfO2 (50Å)/TiN、 Pd/HfO2(25Å)/Pd NCs(7Å)/HfO2 (75Å)/TiN. In this thesis, all switching characteristics, yield, and endurance were exhibited and discussed. A mechanism of local electrical field was proposed to explain these data. Secondly, the nonvolatile memory with sidewall spacer nanaowire was manufactured and TiN nanaocrystals embedded the insulator served as a storage layer. Due to a local electrical field located at a sharp corner of spacer nanowire, the programming and erasing is faster than planer memory. And, the memory window can be improved in proposed nanowire memory device. Keywords: Memory, Nanocrystal, Nanowire, Local electrical field, Yield
目錄 致謝 i 摘要 iii Abstract iv 目錄 v 第一章 緒論 1 1.1 前言 1 1.2 電阻式記憶體 1 1.3 奈米晶粒非揮發記憶體 2 1.4 研究動機 5 1.5 論文結構 6 第二章 非揮發式記憶體操作 11 2.1 電阻式記憶體操作 11 2.2 電阻阻態轉換機制 12 2.2.1 電化學金屬化機制(electrochemical metallization) 12 2.2.2 價數變化電阻轉換機制 (valence change) 13 2.2.3 熱化學機制 (thermo-chemical) 13 2.3 耐久度(Endurance) 13 2.4 電荷保持力(Retention) 14 2.5 非揮發性記憶體元件操作機制 14 2.5.1 穿隧機制 14 2.6 材料分析儀器 15 2.6.1 穿透式電子顯微鏡(TEM) 15 第三章 電阻式記憶體 21 3.1 電阻式記憶體量測方法 21 3.1.1 電阻式記憶體之電流對電壓(I-V)特性曲線 21 3.2 奈米晶粒嵌入介電層之記憶體改善量率與可靠度之研究 21 3.2.1 結果與討論 22 第四章 非揮發性記憶體 36 4.1 非揮發性記憶體元件量測方法 36 4.1.1 汲極電流對閘極電壓(Id-Vg)特性曲線 36 4.2 HfO2 穿隧氧化層之 TiN 奈米晶粒應用在奈米線 TFT 記憶體元件 36 4.2.1 實驗步驟 37 4.2.2 結果與討論 38 第五章 結論 47 5.1 奈米晶粒嵌入介電層中間之電阻式記憶體改善良率 47 5.2 使用 High-K 材料 HfO2 當穿隧氧化層之 TiN 奈米晶粒應用在 TFT 記憶體元件之記憶 特性研究 47 參考文獻 49 圖目錄 圖 1- 1 非揮發記憶體之應用 7 圖 1- 2 RRAM MIM 結構 7 圖 1- 3 浮動閘極記憶體元件 8 圖 1- 4 氮化矽記憶體元件(SONOS) 8 圖 1- 5 奈米晶粒記憶體元件 9 圖 1- 6 沉積數(Å)金屬薄膜立即進行退火自我聚集形成金屬奈米晶粒 9 圖 1- 7 金屬奈米晶粒位能井能帶圖 10 圖 1- 8 奈米晶粒附近產生的局部電場分佈 10 圖 2- 1 單極操作 17 圖 2- 2 雙極操作 17 圖 2- 3 燈絲轉換機制圖 18 圖 2- 4 氧空缺機制圖 18 圖 2- 5 福樂-諾德漢穿隧機制示意圖 19 圖 2- 6 通道熱電子注入機制示意圖 19 圖 2- 7 直接穿隧機制示意圖 20 圖 3- 1 RRAM MIM 四種不同結構 26 圖 3- 2 Pd 金屬沉積在二氧化鉿(TEM) 26 圖 3- 3 Pd 金屬沉積在二氧化鉿局部放大圖(TEM) 27 圖 3- 4 Pd/HfO2(100A)/TiN 量測 I-V 轉換曲線圖 27 圖 3- 5 Pd/HfO2(75A)/Pd(7A)/HfO2(25A)/TiN 量測 I-V 轉換曲線圖 28 圖 3- 6 Pd/HfO2(50A)/Pd(7A)/HfO2(50A)/TiN 量測 I-V 轉換曲線圖 28 圖 3- 7 Pd/HfO2(25A)/Pd(7A)/HfO2(75A)/TiN 量測 I-V 轉換曲線圖 29 圖 3- 8 Pd/HfO2(100A)/TiN 之耐久度圖 29 圖 3- 9 Pd/HfO2(75A)/Pd(7A)/HfO2(25A)/TiN 之耐久度圖 30 圖 3- 10 Pd/HfO2(50A)/Pd(7A)/HfO2(50A)/TiN 之耐久度圖 30 圖 3- 11 Pd/HfO2(25A)/Pd(7A)/HfO2(75A)/TiN 之耐久度圖 31 圖 3- 12 四種結構良率比較圖 31 圖 3- 13 四種結構起始路徑 I-V 曲線圖 32 圖 3- 14 電荷保持力量測 Pd/HfO2(50A)/Pd(7A)/HfO2(50A)/TiN 前五次(寫入/抹除)連續 循環 32 圖 3- 15 電荷保持力量測 Pd/HfO2(50A)/Pd(7A)/HfO2(50A)/TiN 寫入 I-V 曲線圖 33 圖 3- 16 電荷保持力量測 Pd/HfO2(50A)/Pd(7A)/HfO2(50A)/TiN 抹除 I-V 曲線圖 33 圖 3- 17 電荷保持力量測 Pd/HfO2(50A)/Pd(7A)/HfO2(50A)/TiN 寫入/抹除 34 圖 4- 1 TFT 記憶體元件奈米線結構圖 41 圖 4- 2 TFT 奈米線記憶體元件製程流程圖 41 圖 4- 3 TFT 奈米線記憶體元件奈米線製程圖 42 圖 4- 4 TFT 奈米線記憶體元件製程完畢流程圖 42 圖 4- 5 記憶體元件寫入操作示意圖 43 圖 4- 6 記憶體元件抹除操作示意圖 43 圖 4- 7 16 條奈米線記憶體元件寫入/抹除 Id-Vg 曲線圖 44 圖 4- 8 傳統平面式記憶體元件寫入/抹除 Id-Vg 曲線圖 44 圖 4- 9 奈米線記憶體元件模擬電場圖 45 圖 4- 10 4 條奈米線記憶體元件基本寫入/抹除 Id-Vg 曲線圖 45 圖 4- 11 4 條奈米線記憶體元件熱載子寫入/抹除 Id-Vg 曲線圖 46 表目錄 表 3-2-1 RRAM MIM 彙整表 35
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