# 臺灣博碩士論文加值系統

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 在日常生活中的計算都以十進制為基礎做運算，而在對於數位電路計算上卻是以二進制做為其目前最有效的計算方式。但是在使用二進制浮點數進行對於時進制浮點數運算上會發生極大的誤差，因為在二進制浮點數運算是無法精確地表示十進制的浮點數。而今日網路的發達，在網路上進行的交易越來越頻繁，所需的計算要求要更快速及正確。因此，以專門的硬體來實現十進制運算在過去幾年受到極大重視。本論文將針對現有平行十進制乘法器提出改良的設計。預先產生被乘數的倍數，再用以產生整個部分積矩陣，是平行十進制乘法器的主要運作方式。不過，關鍵在於產生幾種倍數，尤其是否產生被乘數的三倍數，會影響產生部分積所需時間與矩陣大小。我們提出兩個改進的設計。首先，我們拆解被乘數，產生長度較短的三倍數，然後再合併成部分積矩陣。另外針對負數倍數，我們提出一個有效率的演算法，降低因為是負數而額外增加的部分積矩陣列數。我們已經在於Cell-Based 環境下以TSMC 0.18um製程完成合成其電路以及功能驗證。結果顯示我們的設計策略確能提高平行十進制乘法器之效能。
 Decimal arithmetic is the way human performs arithmetic. However, it is more natural to implement binary arithmetic in digital electrical circuits. The binary floating-point numbers can only approximate decimal number. To eliminate the conversion error, software is used to do correction. This makes the decimal computation typically 100 to 1000 times slower than binary arithmetic implemented in hardware. Nowadays, commercial, financial and internet-based applications demand higher speed computation and higher accuracy. Hardware realization of decimal arithmetic is becoming a necessity.In recent years many parallel decimal multipliers have been conducted. Generally, a multiplication consists of three stages: (1) partial products (PP) generation, (2) partial products reduction and (3) final conversion from redundant result to non-redundant number. Pre-computing multiples of the multiplicand and then generating the whole partial product matrix is the most popular approach in parallel multipliers. In this paper, we exploit the divide-and-conquer strategy to reduce the latency of the generation of multiples of the multiplicand and keep the row number of PP matrix far less than the 2N, N being the bit width of the multiplier. Furthermore, we propose an efficient algorithm to reduce the extra rows coming from the negative multiples. The design we proposed were synthesized using Synopsys Design Compiler Topographical Technology with TSMC 0.18um library and the results had been verified successfully.
 摘要 i英文摘要 ii誌謝 iii目錄 iv表目錄 vi圖目錄 vii第一章導論 11.1 十進制算術 11.2 二進制VS. 十進制乘法 21.3 論文目的 31.4 論文組織 4第二章十進制算術電路相關研究 52.1 十進制加法 52.2 多位數加法 92.3 十進制乘法 252.4 十進制的進位傳遞加法器 30第三章改進乘法器設計 343.1 已知乘法器之比較 343.2 以分割策略產生三倍數 373.3 合併負數符號值 43第四章電路模擬與合成結果 464.1 設計流程 464.2 電路合成結果 47第五章結論 51參考文獻 52