跳到主要內容

臺灣博碩士論文加值系統

(3.236.84.188) 您好!臺灣時間:2021/08/03 17:01
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:史如琳
研究生(外文):Ju-Lin,Shih
論文名稱:基於有效率產生部份積之平行十進制乘法器
論文名稱(外文):Parallel Decimal Multipliers with Efficient Partial product Generation
指導教授:林寬仁林寬仁引用關係
指導教授(外文):Kuan-Jen Lin
口試委員:盛鐸張昭憲
口試委員(外文):Duo,ShengJau-Shien Chang
口試日期:2013-06-28
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電機工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:61
中文關鍵詞:平行十進制乘法器
外文關鍵詞:Multipliers
相關次數:
  • 被引用被引用:0
  • 點閱點閱:173
  • 評分評分:
  • 下載下載:2
  • 收藏至我的研究室書目清單書目收藏:0
在日常生活中的計算都以十進制為基礎做運算,而在對於數位電路計算上卻是以二進制做為其目前最有效的計算方式。但是在使用二進制浮點數進行對於時進制浮點數運算上會發生極大的誤差,因為在二進制浮點數運算是無法精確地表示十進制的浮點數。而今日網路的發達,在網路上進行的交易越來越頻繁,所需的計算要求要更快速及正確。因此,以專門的硬體來實現十進制運算在過去幾年受到極大重視。
本論文將針對現有平行十進制乘法器提出改良的設計。預先產生被乘數的倍數,再用以產生整個部分積矩陣,是平行十進制乘法器的主要運作方式。不過,關鍵在於產生幾種倍數,尤其是否產生被乘數的三倍數,會影響產生部分積所需時間與矩陣大小。我們提出兩個改進的設計。首先,我們拆解被乘數,產生長度較短的三倍數,然後再合併成部分積矩陣。另外針對負數倍數,我們提出一個有效率的演算法,降低因為是負數而額外增加的部分積矩陣列數。我們已經在於Cell-Based 環境下以TSMC 0.18um製程完成合成其電路以及功能驗證。結果顯示我們的設計策略確能提高平行十進制乘法器之效能。

Decimal arithmetic is the way human performs arithmetic. However, it is more natural to implement binary arithmetic in digital electrical circuits. The binary floating-point numbers can only approximate decimal number. To eliminate the conversion error, software is used to do correction. This makes the decimal computation typically 100 to 1000 times slower than binary arithmetic implemented in hardware. Nowadays, commercial, financial and internet-based applications demand higher speed computation and higher accuracy. Hardware realization of decimal arithmetic is becoming a necessity.
In recent years many parallel decimal multipliers have been conducted. Generally, a multiplication consists of three stages: (1) partial products (PP) generation, (2) partial products reduction and (3) final conversion from redundant result to non-redundant number. Pre-computing multiples of the multiplicand and then generating the whole partial product matrix is the most popular approach in parallel multipliers. In this paper, we exploit the divide-and-conquer strategy to reduce the latency of the generation of multiples of the multiplicand and keep the row number of PP matrix far less than the 2N, N being the bit width of the multiplier. Furthermore, we propose an efficient algorithm to reduce the extra rows coming from the negative multiples. The design we proposed were synthesized using Synopsys Design Compiler Topographical Technology with TSMC 0.18um library and the results had been verified successfully.

摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章導論 1
1.1 十進制算術 1
1.2 二進制VS. 十進制乘法 2
1.3 論文目的 3
1.4 論文組織 4
第二章十進制算術電路相關研究 5
2.1 十進制加法 5
2.2 多位數加法 9
2.3 十進制乘法 25
2.4 十進制的進位傳遞加法器 30
第三章改進乘法器設計 34
3.1 已知乘法器之比較 34
3.2 以分割策略產生三倍數 37
3.3 合併負數符號值 43
第四章電路模擬與合成結果 46
4.1 設計流程 46
4.2 電路合成結果 47
第五章結論 51
參考文獻 52

[1]W. Buchholz, “Fingers or Fists? (The Choice of Decimal or Binary representation),” Communications of the ACM, vol. 2, no. 2, pp. 3-11, 1959.
[2]IBM Corporation, “Decimal Arithmetic FAQ,”
http://speleptrove.com.com/decimal/decifaq1.html, 2007.
[3]M. F. Cowlishaw, “Decimal Floating-Point: Algorism for Computers,” Proc. 16th IEEE Symp. Computer Arithmetic, pp. 104-111, 2003.
[4]IEEE Standard for Floating-Point Arithmetic, IEEE Working Group of the Microprocessor Standards Subcommittee, IEEE, 2008.
[5]E. M. Schwarz, J. S. Kapernick and M. F. Cowlishaw, “Decimal Floating-point Support on the IBM System z10 Processor,” IBM Journal of Research and Development, vol. 53. no. 1, pp. 4:1-4:10, 2009.
[6]S. Carlough, A. Collura, S. Mueller and M. Kroener, “The IBM zEnterprize-196 Decimal Floating-Point Accelerator,” Proc. the 20th IEEE Symposium on Computer Arithmetic, pp. 139-146, 2011.
[7]M. A. Erle and M. J. Schulte, “Decimal Multiplication Via Carry- Save Addition,” Proc. 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors, pp. 348-358, 2003.
[8]M. A. Erle, M. A. Schwarz and M. J. Schulte, “Decimal Multiplication with Efficient Partial Product Generation,” Proc. 17th IEEE Symposium on Computer Arithmetic, pp. 21-28, 2005.
[9]M. A. Erle, B. J. Hickmann and M. J. Schulte, “Decimal Floating-Point Multiplication,” IEEE Trans. Computers, vol. 58, no. 7, pp. 902-916, 2009.
[10]A. Vazquez, E. Antelo and P. Montuschi, “A New Family of High-Performance Parallel Decimal Multipliers,” Proc. 18th IEEE Symposium Computer Arithmetic (ARITH ’07), pp. 195-204, 2007.
[11]A. Vazquez, “High-Performance Decimal Floating-Point Units,” PhD. Dissertation, Department of Electrical Engineering, Univeraidade de Santiago de Compostela, 2009.
[12]A. Vazquez, E. Antelo and P. Montuschi, “Improved Design of High-Performance Parallel Decimal Multipliers,” IEEE Trans. on Computers, pp. 679-693, May 2010.
[13]T. Lang and A. Nannmarelli, “A Radix-10 Combinational Multiplier,” Proc. 40th Asilomar Conf. Signals, Systems, and Computers, pp. 313-317, 2006.
[14]R. K. James, T. K. Shahana, K. Poulose Jacob and Sreela Sasi, “Fixed Point Decimal Multiplication using RPS Algorithm,” Proc. International Symposium on Parallel and Distributed Processing with Applications, pp. 343-350, 2008.
[15]G. Jaberipur and A. Kaivani, “Binary-Coded Decimal Digit Multiplier,” IET Computers & Digital Techniques, vol. 1, Issue 4, pp. 377-381, 2007.
[16]G. Jaberipur and A. Kaivani, “Improving the Speed of Parallel Decimal Multiplication,” IEEE Transactions on Computers, vol. 58, no. 11, pp. 1539-1552, 2009.
[17]S. G. Navarro, C. Tsen and M. J. Schulte, "A Binary Integer Decimal-Based Multiplier for Decimal Floating-Point Arithmetic," Proc. 41th Asilomar Conference on Signals, Systems, and Computers, 2007.
[18]M. F. Cowlishaw, “Densely Packed Decimal Encoding,” IEE Proceedings - Computers and Digital Techniques, vol. 149, no. 3, pp. 102-104, 2002.
[19]C. Tsen, S. G. Navarro and M. J. Schulte, “Hardware Design of a Binary Integer Decimal-based Floating-point Adder,” Proc. IEEE International Conference on Computer Design, pp. 288-295, Oct. 2007.
[20]C. Tsen, S. G. Navarro and M. J. Schulte, “Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit,” Proc. IEEE International International Conference on Application-specific Systems, Architectures and Processors, July 2007.
[21]M. S. Schmookler and A.W. Weinberger, “High Speed Decimal Addition,” IEEE Trans. Computers, vol. 20, no. 2, pp. 862-867, 1971.
[22]Behrooz Parhami, Computer Arithmetic Algorithms and Hardware Designs, Oxford University Press, 2000.
[23]S. Gorgin and G. Jaberipur, “Fully Redundant Decimal Arithmetic,” Proc. 19th IEEE International Symposium on Computer Arithmetic, pp. 145-152, 2009.
[24]R. D. Kenney and M. J. Schulte, “High-Speed Multioperand Decimal Adders,” IEEE Transactions on Computers, vol. 54, no. 8, pp. 953-963, 2005.
[25]L. Dadda, “Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach,” IEEE Transactions on Computers, vol. 56, no. 9, pp. 1320-1328, 2007.
[26]I. D. Castellanos and J. E. Stine, “Compressor Trees for Decimal Partial Product Reduction,” Proc. Great Lakes Symposium on VLSI Systems, pp. 107-110, 2008.
[27]B. J. Hickmann, A. K., M. J. Schulte and M. A. Erle, “ A Parallel IEEE P754 Decimal Floating-Point Multiplier,” Proc. IEEE International Conference on Computer Design , pp. 296-303, 2007.
[28]K. J. Lin, Y. C. Chiu and T. H. Lin, “A Decimal Squarer with Efficient Partial Product Generation,” Proc. 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, pp. 213-218, 2010.
[29]L. K. Wang, M. J. Schulte, J. D. Thompson and N. Jairam, “Hardware Designs for Decimal Floating-Point Addition and Related Operations,” IEEE Transactions on Computers, pp. 322-335, Mar. 2009.
[30]R. Manohar and J. Tierno, “Asynchronous Parallel Prefix Computation,” IEEE Transactions on Computers, vol. 47, no. 11, pp. 1244-1252, Nov. 1998.
[31]F. C. Cheng, Stephen H. Unger and M. Theobald, “ Self-Timed Carry-Lookahead Adders,” IEEE Transactions on Computers, vol. 49, no. 7, pp. 659-672, July 2000.
[32]J. Rebacz, E. Oruklu and J. Saniie, “Performance Evaluation of Multi-Operand Fast Decimal Adders,” Proc. IEEE Midwest Symposium on Circuits and Systems, pp. 535-538, 2009.
[33]M. P. Vestias and H. C. Neto, “Parallel Decimal Multipliers Using Binary Multipliers,” Proc. Programmable Logic Conference, pp. 73-78, 2010.
[34]J. Sparso and S. Furber, Principles of Asynchronous Circuit Design, Kluwer Academic Publishers, 2001.
[35]K. J. Lin, J. L. Shih, T. H. Lin and Y. M. Wang, ” A Parallel Decimal Adder with Carry Correction during Binary Accumulation,” Proc. IEEE New Circuits and Systems International Conference, Montreal, Canada, pp. 104-107, 2012.
[36]K. J. Lin, J. L. Shih, T. H. Lin and Y. M. Wang, ” Combined Decimal/Binary Multi-Operand Addition with Efficient Carry Correction,” Proc. the 23th VLSI Design/CAD Symposium, Kenting, 2012.
[37]J. Rebacz, E. Oruklu and J. Saniie, “High Performance Signed-Digit Decimal Adders,” Proc. IEEE International Conference on Electro/Information Technology, pp. 251-255, 2009.
[38]M. Baesler, S. O. Voigt and T. Teufel, “An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier,” Proc. IEEE International Conference on Field Programmable Logic and Applications, pp. 489-495, 2010.
[39]O. Al-Khaleel, Z. Al-qudah, M. Al-Khaleel, C. A. Papachristou and F. G. Wolff “Fast and Compact Binary-to-BCD Conversion Circuits for Decimal Multiplication,” Proc. IEEE 29th International Conference on Computer Design, pp. 226-231, 2011.
[40]A. Aswal, M.G. Perumal and G.N.S. Prasanna “On Basic Financial Decimal Operations on Binary Machines,” IEEE Transactions on Computer, vol. 61, no. 8, pp. 1084-1096, 2012.
[41]B. Dilli Kumar and M. Bharathi, “A High Speed and Efficient Design for Binary Number Squaring Using Dwandwa Yoga,” International Journal of Advanced Research in Computer Engineering & Technology, vol. 1, Issue 4, pp. 476-479, June 2012.
[42]L. Han and S. B. Ko, “High-Speed Parallel Decimal Multiplication with Redundant Internal Encoding,” IEEE Transactions on Computer, vol. 62, no. 5, pp. 956-968, 2013.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top