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研究生:張敬宗
研究生(外文):Jing-Zong Jhang
論文名稱:(100)或(110)矽晶格基板上之奈米CESL應變於pMOSFETs元件偏壓效應研究
論文名稱(外文):Body Effect of Nano-regime CESL Strained pMOSFETs on (100) or (110) Si Wafers
指導教授:王木俊王木俊引用關係
指導教授(外文):Mu-Chun Wang
口試委員:劉傳璽王錫九
口試委員(外文):Chuan-Hsi LiuShea-Jue Wang
口試日期:2013-06-28
學位類別:碩士
校院名稱:明新科技大學
系所名稱:電子工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:84
中文關鍵詞:單軸應變雙軸應變遷移率基板偏壓效應接觸蝕刻停止層
外文關鍵詞:uni-axial strainbi-axial strainmobilityCESLbody effect
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在遵循摩爾定律(Moore’s law)的原則下,隨著半導體生產技術快速地發展,金氧半場效電晶體(Metal-oxide-semiconductor field-effect transistor, MOSFET)已從100微米的世代進入到目前主流量產為45奈米或先進少量量產之20奈米世代。這幾年來,為了提升了金氧半場效電晶體之驅動電流,在尺寸微縮時,漸漸地在微影製程技術方面遇到了瓶頸。因此,思索其他可提升驅動電流的解決方式是有其必要的。其中之一為應變工程技術,利用此關鍵技術以提升載子移動率(Carrier mobility) ,進而改善驅動電流的大小值。此應變技術是利用矽與鍺的晶格常數不同,而產生匹配不均,來產生電晶體通道(矽鍺通道)應變,應變工程一般可分為二種:單軸應變(Uniaxial strain)也稱局部應變(Local strain)和雙軸應變(Biaxial strain)亦稱全面應變(Global strain)。因為n/pMOSFET元件對於應變通道的需求有所不同,以單軸應變在X、Y、Z三方向,會得到不一樣的載子遷移率變化,分別提高電子或電洞之遷移率而有可能被導入量產。
由文獻指出,X、Y平面在拉伸應力下,電子或電洞的載子遷移率(Mobility),著實貢獻不少。對於p通道元件而言,電洞的載子遷移率的增加是有效載質量(Effective mass)的減少; 對於n通道元件電子遷移率提高而言,則為載子在電子的谷間散射(Inter-valley scattering)情形和能帶間的散射(Inter-band scattering )情形減少有關,此等反應即是平均碰撞時間(Mean free time)的增加,進而提升此載子遷移率。
本研究之主題在討論矽覆蓋層於(100)或(110)矽晶格基板上pMOSFETs元件之偏壓效應研究。當我們利用基板加偏壓時,可以分析通道反轉層電荷分佈,尤其對夾層中的嵌入矽鍺通道結構是有幫助的。本次實驗中,利用接觸蝕刻停止層(CESL),作為元件的應變的來源,探討pMOSFETs元件於拉伸應變與壓縮應變下之電特性變化,並討論在不同晶格(100)或(110)的pMOSFETs元件時與傳統無應變電晶體做比較。
關鍵字: 單軸應變、雙軸應變、遷移率、基板偏壓效應、接觸蝕刻停止層

With the rapid growth of semiconductor production technology, the feature size of metal-oxide-semiconductor field-effect transistor (MOSFET) narrows down from 100 m to 45nm mass production or 20nm generation in pilot run due to Moore's law. Recently, besides the shrinkage of device facing some bottlenecks, especially in photo-lithography, thinking some alternative to overcome these barriers is necessary. One of feasible processes is strain engineering. Using this technology, the mobility of channel carrier can be impressively improved in drive current. Adopting the mismatch of lattice constants between silicon and germanium generates some strain in channel. In generally, there are two popular strain processes: uni-axial (local) strain and bi-axial (global) strain. Because the contribution of strain for n/pMOSFETS in three dimensions (X, Y and Z) is different, the mobility values with local strain technology are also various. When the mobility of channel electron or hole is able to be separately promoted, the chance in IC mass production is increased.
In the published literatures, the discussion of mobility of electron or hole under in-plane tensile strain was described well. For the increase of mobility of channel hole, the main ratio comes from the contribution of light hole with the lighter effective mass. Conversely, for the improvement of electron mobility is due to the reduction of electron carrier inter-valley scattering and inter-band scattering, which means the increase of mean free time.
In this work, the main focus is to study the body effect of nano-regime CESL strained pMOSFETs on (100) or (110) Si wafers. When the substrate is biased, the distribution of surface channel charges in inversion mode can be probed and helpfully analyzed, related to the integrity of embedded SiGe layer. Using contact-etch-stop-layer (CESL) processes as strain resources including tensile and compressive effects on (100) or (110) wafers is the other impressive topic to realize the strain relationship among non-strained, compressive and tensile tested devices.
Keywords: uni-axial strain, bi-axial strain, mobility, CESL, body effect.

目錄
摘要 I
誌謝 V
表目錄 VIII
圖目錄 IX
第一章 緒論 1
1.1簡介 1
1.2 研究動機 2
第二章 元件物理概論 3
2.1能帶(energy)與能隙(energy gap)架構 3
2.2 P-N接面的基本結構與特性 4
2.3偏壓與內建電位 6
2.4電場分析與空乏區寬度 8
2.6理想的MOS元件能帶圖 13
2.6.1聚積 (Accumulation) 13
2.6.2空乏 (Depletion) 14
2.6.3反轉 (Inversion) 14
2.7 金氧半場效電晶體基本特性 16
2.8理想MOSFET的I-V特性 18
2.9 IDSVSVDS方程式推導 19
2.10轉移特性(Transfer characteristics) 22
2.11其他重要元件參數 24
2.11.1臨界電壓 24
2.11.2次臨界特性 ( Subthreshold characteristics ) 25
2.11.3遷移率退化 (mobility degradation) 27
2.11.4基板偏壓效應(body effect) 28
2.12短通道效應 29
2.12.1通道長度調變效應 30
2.12.2臨界電壓下滑(Threshold voltage roll-off) 32
2.12.3汲極引發的能障下降 34
2.12.4貫穿(Punch-through) 35
第三章 應變元件 37
3.1應變矽元件簡介 37
3.2全面性應變矽元件特性 37
3.2.1全面性應變矽之物理機制 39
3.3局部性應變矽元件特性 40
3.3.1非等比例成長與等量成長 44
3.3.2贋晶或假晶成長 45
3.4 應變矽元件面臨之問題 47
3.5 應變矽元件應用 48
第四章 實驗與結果 49
4.1整體實驗架構說明 49
4.1.1 八寸半導體手動探針量測平台( probe station) 50
4.1.2半導體參數分析儀Agilent 4156C 51
4.1.3 Agilent E5250A 52
4.2 元件介紹 53
4.3 實驗條件 55
4.3.1 |ID|-VD特性曲線 55
4.3.2 |ID|-VG特性曲線 55
4. 4 實驗結果 56
4. 4.1 大尺寸實驗 56
4. 4.1.1 大尺寸之|ID|-VD特性曲線 56
4. 4.1.2 大尺寸之|ID|-VG特性曲線 58
4. 4.1.3 大尺寸之GM-VG特性曲線 59
4. 4.1.4 大尺寸之Gamma曲線圖 61
4. 4.2. 小尺寸實驗 66
4. 4.2.1 小尺寸之|ID|-VD特性曲線 66
4. 4.2.2 小尺寸之|ID|-VG特性曲線 69
4. 4.2.3 小尺寸之GM-VG特性曲線 71
4. 4.2.4 小尺寸之Gamma曲線圖 72
第五章 結論 76
參考文獻 78
作者簡介 82

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