(3.234.221.162) 您好!臺灣時間:2021/04/14 04:49
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

我願授權國圖
: 
twitterline
研究生:鄭有成
研究生(外文):Yu-Cheng Cheng
論文名稱:應用於TLB中之電荷平衡標籤記憶體設計
論文名稱(外文):Charge Balance Tag Memory Design Used in TLB
指導教授:張延任
指導教授(外文):Yen-Jen Chang
口試委員:林英超蔡坤霖
口試日期:2013-01-14
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學與工程學系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:62
中文關鍵詞:內容可定址記憶體位址轉換暫存器電荷平衡
外文關鍵詞:Content Addressable MemoryTranslation Lookaside BufferCharge Balance
相關次數:
  • 被引用被引用:0
  • 點閱點閱:121
  • 評分評分:系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔系統版面圖檔
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
內容可定址記憶體(Content Addressable Memory, CAM)是一種能平行搜尋比對的儲存元件,經常使用於位址轉換暫存器(Translation Lookaside Buffer, TLB),然而每次資料比對搜尋,往往只有一筆或少數筆資料與欲搜尋之資料相符,使得CAM之相符線(match line)頻繁地充放電,造成大量的功率消耗;而TLB每次的資料比對搜尋,只會有一筆甚至沒有任何資料與欲搜尋之資料相符合,導致更大的功率消耗。在本篇論文中,藉由N型內容可定址記憶體(N-CAM)與P型內容可定址記憶體(P-CAM)的相符線充放電行為互補之特性,我們提出一種自動電荷平衡機制(Charge Balance)應用於TLB tag,使相符線之間電荷平衡,降低相符線電壓擺幅,以減少動態功率消耗。使用台積電90奈米製程,於室溫25℃與供應電壓1.2V下做模擬。實驗結果顯示,與傳統設計相比,採用自動電荷平衡機制可節省27.24%的動態功率消耗。

Content Addressable Memory (CAM) is a kind of high fast memory which can perform parallel comparison but consumes large power, since only a few cases are matched in every data search. However, the translation lookaside buffer (TLB), which consists of CAMs and SRAMs, suffers from more power consumption because there is at most one word matched in every TLB search. That is, at most one match line (ML) of CAM stays in the VDD level, but the others would be discharge to GND level. We proposed the charge balance (CB) technique, which based on the complementary operation of N-type CAM (N-CAM) and P-type CAM (P-CAM), to reduce the dynamic power consumption in MLs. In our design, the TLB consists of N-CAM arrays and P-CAM arrays, and the MLs of N-CAM (N-MLs) would connect with the MLs of P-CAM (P-MLs) by the CB bridge. The CB technique can automatically balance the charge of P-MLs and the corresponding N-MLs without additional signal. The TLB tag with the CB technique reduces the dynamic power consumption by 27.24% compared with the traditional design which simulated in TSMC 90 nm technique.

中文摘要 i
英文摘要 iii
目錄 v
表格目錄 vi
圖目錄 vii
1、 簡介 1
2、 虛擬記憶體(Virtual Memory) 3
2.1. 分頁表(Page Table) 3
2.2. 位址轉換暫存器(Translation Lookaside Buffer) 5
3、 內容可定址記憶體(Content Addressable Memory)架構 8
3.1. 傳統CAM之架構 8
3.2. NOR型式CAM之架構 10
3.3. NAND型式CAM之架構 12
3.4. 相關研究 17
3.4.1. 參考文獻[9] 18
3.4.2. 參考文獻[10] 20
3.4.3. 參考文獻[11] 21
3.4.4. 參考文獻[12] 24
4、 相符線自動電荷平衡架構(Charge Balance Technique) 28
4.1. P型內容可定址記憶體(P-CAM) 28
4.2. NOR型式P-CAM之架構 35
4.3. 自動電荷平衡相符線架構 38
4.4. Dummy P型相符線(Dummy P-Type Match Line, DP-ML) 46
5、 實驗結果分析 49
5.1. CB技術功能正確性 50
5.2. 動態功率消耗分析 53
5.3. 電荷平衡時間與功率消耗之關係 56
6、 結論 59
7、 未來展望 60
8、 參考文獻 61



[1] Chia-Cheng Chen, Hung-Yu L, and Jinn-Shyan Wang, “The Split-Path AND-type Match-line Scheme for Very High-Speed Content Addressable Memories,” IEEE Asian Solid-State Circuits Conference, pp.525-528, 2005.

[2] Sheng-Ping Yong, Jin-Fu Li, and Yu-Jen Huang, “Variability-Tolerant Binary Content Addressable Memory Cells,” IEEE International Workshop on Memory Technology, Design, and Testing, pp.44-49, 2009.

[3] Yu-Ting Pai, Chia-Han Lee, Shanq-Jang Ruan and Edwin Naroska, “An Improved Comparison Circuit for Low Power Pre-computation-Based Content-Addressable Memory designs,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp.663-666, 2009.

[4] Igor Arsovski and Ali Sheikholeslami, “A Current-Saving Match-Line Sensing Scheme for Content-Addressable Memories,” IEEE International Solid-State Circuits Conference (ISSCC), pp.304-305, 2003.

[5] V. Chaudhary, T.-H. Chen, F. Sheerin and L.T. Clark, “Critical race-free low-power NAND match line content addressable memory tagged cache memory,” IET Computers & Digital Techniques, Vol. 2, No. 1, pp.40-44, January 2008.

[6] Yen-Jen Chang, Yuan-Hong Liao and Shanq-Jang Ruan, “Improve CAM Power Efficiency Using Decoupled Match Line Scheme,” Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.1-6, 2007.

[7] Yen-Jen Chang and Yuan-Hong Liao, “Hybrid-Type CAM Design for Both Power and Performance Efficiency,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.16, No. 8, pp.965-974, August 2008.

[8] Deepak S Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh and Poras T. Balsara, “Ripple-Precharge TCAM: A Low-Power Solution for Network Search Engines,” IEEE International Conference on Computer Design (ICCD), pp.243-248, 2005.

[9] Amit Agarwal, Steven Hsu, Sanu Mathew, Mark Anders, Himanshu Kaul, Farhana Sheikh and Ram Krishnamurthy, “A 128x128b High-Speed Wide-AND Match-Line Content Addressable Memory in 32nm CMOS,” IEEE Proceedings of the European Solid-State Circuits Conference (ESSCIRC), pp.83-86, 2011.

[10] Anh Tuan Do, Shoushun Chen, Zhi-Hui Kong and Kiat Seng Yeo, “A Low-Power CAM with Efficient Power and Delay Trade-off,” IEEE International Symposium on Circuits and Systems (ISCAS), pp.2573-2576, 2011.

[11] Nitin Mohan and Manoj Sachdev, “Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs,” IEEE Journal of Solid-State Circuits, Vol.42, No. 9, pp.2054-2060, September 2007.

[12] Takahito Kusumoto, Daisuke Ogawa, Katsumi Dosaka, Masayuki Miyama, and Yoshio Matsuda, “A Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications,” IEEE Asian Solid-State Circuits Conference, pp.253-256, 2008.

[13] Jian-Wei Zhang, Yi-Zheng Ye, Bin-Da Liu, Feng Guan, “Self-Timed Charge Recycling Search-Line Drivers in Content-Addressable Memories,” IEEE International Symposium on Circuits and Systems (ISCAS), pp.3070-3073, 2009.

[14] David A. Patterson and John L. Hennessy, “Computer Organization and Design: The Hardware/Software Interface, 4/e,” Morgan Kaufmann publishers, Inc., 2008.

[15] Abraham Silberschatz, Peter B. Galvin and Greg Gagne, “Operating Systems Concepts, 8th Edition,” John Wiley & Sons. Inc, 2009.

[16] Cadence Design Systems Inc., “Virtuoso Layout Editor Users Guide-Version 4.4.6. ” June 2000.

[17] National Chip Implementation Center, http://www.cic.org.tw.


QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
系統版面圖檔 系統版面圖檔