臺灣博碩士論文加值系統

本論文在描述如何用90nm製程實現與設計60-GHz頻率合成器，當中包含四相位壓控振盪器(QVCO)、倍頻器(FD)以及高速除頻器。其中倍頻器提供46.8到48.8GHz(4.18%)的頻率輸出範圍。模擬48GHz二倍頻的載波頻率的相位誤差為-95.71 dBc/Hz在1-MHz偏差處，同時在四相位壓控振盪器主要頻率輸出頻率的相位誤差為-96.01 dBc/Hz在1-MHz偏差處。其整個電路功耗低於55mW在Vdd為1.2V時。
本論文主要分成三部分，首先介紹鎖相迴路的概念以及研究動機和應用的規範，尤其60GHz的部分會特別說明。
接著會就各個子電路來做分析及模擬，特別是QVCO的部分，說明如何分析並且設計低雜訊，和pulse swallow counter 部分，闡述如何設計可以除高頻、低功耗並且達到高解度，還有倍頻器如何達利用電流重複利用以及利用其對稱性降低其雜訊。
最後一部分針對晶片的量測考量，以及說明軟體間差異，還有寄生效應評估來做解說，並且針對未來可以研究改善的課題加以討論。

The paper describes the design and realization of a quadracture voltage-controlled oscillator (QVCO), a frequency doubler (FD) and a high-speed frequency divider for a 60-GHz RF frequency synthesizer that has been implemented with 90nm CMOS technology. The FD provides the tuning range of 46.8 to 48.8 GHz (4.18%). At 48GHz carried frequency with doubling-frequency operation, the simulated phase noise is -95.71 dBc/Hz at 1-MHz offset. Simultaneously, the fundamental frequency output by the QVCO provides the phase noise of -96.01dBc/Hz at 1-MHz offset. The core circuit dissipates below 55mW at a 1.2V supply.
This paper is divided into three parts, first introduced the concept of phase-locked loop , and research motivation and norms, especially the part 60GHz''s application will be particularly described.
Then will do the various sub-circuit analysis and simulation, especially QVCO part explains how to analyze and design of low noise, and pulse swallow counter part, explains how to design divide high-frequency, low power consumption and high resolution, and use current reusing doubler and let its symmetry to reduce noise.
Last part of the consideration for wafer measurements, as well as explain the difference between the software, and parasitic effects assessment to do commentary, and improvement for future research topics can be discussed.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 ix
第１章 緒論 1
1.1 研究動機 1
1.2 24-GHz和60-GHz的應用 3
1.3 論文架構 5
第２章 鎖相迴路簡介 6
2.1 鎖相迴路簡介 6
2.2 PFD、CP及LPF電路與原理 7
2.2.1 相位頻率偵測器(Phase Frequency Detector, PFD)[6] 8
2.2.2 充電泵(Charge Pump, CP)[7] 10
2.2.3 迴路濾波器(Loop Filter, LPF) 11
2.3迴路特性 14
2.3.1 相位雜訊分析[8][9][10] 14
2.3.2 Reference Spur[11] 25
2.3.3 迴路分析 27
2.3.4 迴路設計流程 29
2.4 PFD和Charge Pump模擬 30
第３章 壓控振盪器、倍頻器以及除頻器的分析與設計 31
3.1 四相位壓控振盪器(QVCO)設計[12][13] 31
3.2 倍頻器設計[14][15] 42
3.3 倍頻器和QVCO的振幅、頻率及相位雜訊模擬 44
3.4 Pulse Swallow Counter 設計 47
3.5 其他除頻器探討 52
3.6 除頻器模擬 53
3.6.1 Divider by 4(LC Tank Oscillator)模擬 53
3.6.2 Divider by 4(Ring Oscillator)結合Phase Rotate模擬 54
3.6.3 Pulse Swallow Counter 模擬 56
3.7頻率合成器模擬 57
第４章 量測 58
4.1 量測考量 58
4.2 量測結果 62
第５章 結論與未來展望 66
5.1 比較與結論 66
5.2 未來展望 67
參考文獻 68

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