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研究生:廖國翔
研究生(外文):Kuo-Hsiang Liao
論文名稱:超高壓功率元件800V LDMOS特性分析與設計
論文名稱(外文):Analysis and design of high power 800v LDMOS characteristics
指導教授:游信強游信強引用關係
指導教授(外文):Hsin-Chiang You
學位類別:碩士
校院名稱:國立勤益科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:72
中文關鍵詞:高壓元件崩潰電壓N-DriftSOI摻雜
外文關鍵詞:High-voltage DeviceBreakdown VoltageN-DriftSOIDoping
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在市場上應用在各種地方,以電腦來說筆記型電腦要求輕薄短小化,如何減輕電源供應器的體積功率元件是不可以缺少的,如此的需求也帶領著POWER MOSFET的發展,在未來科技的進步此種趨勢以及技術的進步將會永無止境延伸與改進功率元件的特性。
藉由Tsuprem-4跟Medici模擬軟體,分別用來模擬元件的製程結構和電性模擬,以獲得最佳的製程參數利用不同的N-Drift長度、不同Dose濃度及濃度梯度來改變其崩潰電壓(Breakdown Voltage),這將是要深入探討的主要內容,本論文所做的研究即為 LDMOS-800V高壓元件,它的形式基本上有水平式及垂直式兩種,其中縱向結構以溝槽式閘極功率電晶體為代表,橫向結構則以雙擴散金氧半場效電晶體為為代表。本論文中將討論雙擴散金氧半場效電晶體特性及運用線性摻雜的原理在絕緣層上使用矽晶結構(SOI),來製程所需要的LDMOS 800V並比較其差異性。
使用Tsuprem-4模擬所需要的電壓數值,也驗證了N-Drift的長度越長崩潰電壓越大、摻雜的濃度的改變也可以控制崩潰電壓,日常生活電器最大伏特數是220V,而本文所做的Bulk LDMOS是可以達到807V的Off-State Voltage,然而本文的On-State Voltage大約可以承受709V的電壓,因此在安全方面是沒有問題的。當閘極施加電壓1V時可以看出的空乏區比較大,本文所模擬出來電壓可以承受接近800V,而當閘極施加電壓5V時可以看出空乏區比較小,本文所模擬出來電壓可以承受接近700V,故空乏區越大耐壓越大,空乏區越小耐壓越小,因此本文所做的LDMOS高壓元件將不會有安全上的顧慮。

For the applications on the market in a variety of places, a thin, light weight notebook computer absolutely essential to reduce the volume of power and components of the power supply. Such demand also led to the development of POWER MOSFET. In the future technology progress advances and trends, it will be endless extension and improvement of the power element characteristics.
Tsuprem-4 with Medici simulation software were used to simulate the components of the process structure and electrical simulation to obtain the best process parameters by which different N-Drift long level combined with different Dose concentration and different ladder degree used to change the breakdown voltage, which is main content for depth discussion .
The paper presented shall be the LDMOS-800V high voltage components, which have two forms basically, Horizontal and vertical. This paper will discuss the double-diffused metal-oxide-semiconductor field-effect transistor characteristics and the use of linear doping principles used in the insulating layer silicon the structural (SOI), which are used to process the required LDMOS 800V and to compare the differences.
Tsuprem-4 was used to simulate the required voltage, but also verify that the longer the length of the N-Drift, the larger the breakdown voltage, and changing the dopant concentration can also control the breakdown voltage. The maximum electrical voltage used in daily life is 220V. However, Bulk LDMOS fabricated and then simulated in this paper can reach 807V Off-State Voltage, and, also, On-State Voltage approximately withstands 709V, so there is no problem in terms of safety. When the gate voltage is applied 1V, the depletion region obviously appears and becomes wider. The simulated voltage in this paper can withstand close to 800V. The depletion region is relatively smaller when the gate voltage 5V is applied. The simulated LDMOS high voltage device proposed by this paper can withstand near 700V voltage. The greater the depletion region, the larger the withstand voltage; the smaller the depletion region, the smaller the withstand voltage. Therefore, there are no safety concerns for the LDMOS high voltage device fabricated in this paper.

中文摘要------------------------------------Ⅵ
英文摘要------------------------------------Ⅶ
誌謝----------------------------------------Ⅸ
目錄----------------------------------------Ⅹ
表目錄--------------------------------------ⅩⅢ
圖目錄--------------------------------------ⅩⅣ
第一章 緒論-------------------------------1
1.1 功率元件特性與應用---------------------1
1.2 論文架構------------------------------3
第二章 文獻探討----------------------------4
2.1 軟體介紹------------------------------4
2.1.1 Tsuprem-4介紹----------------------4
2.1.2 Medici介紹-------------------------5
2.1.3 Linux介紹--------------------------6
2.2 LDMOS與LIGBT差異---------------------7
2.2.1 LDMOS(Laterally Diffused Metal Oxide Semiconductor) ----------------------------7
2.2.2 LIGBT(Laterally Insulated Gate Bipolar Transistor) --------------------------------7
2.2.3 LDMOS與LIGBT比較--------------------8
2.3 LDMOS元件特性-------------------------9
2.3.1 影響LDMOS崩潰電壓的主因--------------9
2.3.2 LDMOS元件優勢-----------------------9
2.4 SOI介紹------------------------------10
2.4.1 SOI MOSFET操作原理-----------------10
2.4.2 SOI材料與晶圓製作-------------------11
2.5 LDMOS-800V應用-----------------------13
2.6 元件的發展----------------------------15
2.6.1 垂直式元件的發展---------------------17
2.6.2 橫向式元件的發展---------------------17
2.7 磊晶層厚度對元件影響-------------------18
2.8 功率電晶體模擬推導---------------------18
第三章 製程步驟----------------------------20
3.1 Bulk Si製程步驟-----------------------20
3.2 SOI製程步驟---------------------------30
第四章 電性分析----------------------------40
4.1 崩潰電壓分析---------------------------40
4.1.1 Bulk Si基板崩潰電壓分析--------------40
4.1.2 SOI基板潰電壓分析--------------------41
4.2 電場與電流分析-------------------------43
4.2.1 Bulk Si基板電場與電流分析------------43
4.2.2 SOI基板電場分析---------------------49
4.3 空乏區與電位分析-----------------------56
4.3.1 Bulk Si基板空乏區與電位分析----------56
4.3.2 SOI基板空乏區與電位分析--------------62
第五章 結論-------------------------------68
參考文獻------------------------------------69

[1]Baliga B.J., “The future of power semiconductor device technology”, Proceedings of the IEEE, Vol. 89, pp. 822-832, 2001.
[2]Baliga B.J., “Trends in power semiconductor devices”, Electron Devices, Vol. 43, pp. 1717-1731, 1996.
[3]B. Jayant Baliga, “Fundamentals of Power Semiconductor Devices”, 2008.
[4]莊達人,“VLSI製造技術”,高立圖書,2008。
[5]Hong Xiao,“半導體製程技術導論”,台灣培生教育,2007。
[6]Michael Quirk,“半導體製造技術”,滄海書局,2007。
[7]陳盈淙,“CMOS淺溝槽隔離氧化層之高度差對元件特性之研究”,國立清華大學,2007。
[8]F.J. Yang, J.L. Tsay, C.C. Cheng, R.S. Liou, H.C. Tuan, “State-of-the-art device in high voltage power ICs with lowest on-state resistance”, Electron Devices Meeting (IEDM), pp.20.8.1-20.8.4, 2010.
[9]Guangjun Cao , Manhas S.K. , Narayanan E.M.S. , De Souza M.M. , Hinchley D. ,“Comparative study of drift region designs in RF LDMOSFETs”, Electron Devices, Vol. 51, pp.1296-1303, 2004.
[10]Mandegaran S., Hajimiri A., “A Breakdown Voltage Multiplier for High VoltageSwing Drivers”, Solid-State Circuits, Vol. 42, pp.302-312, 2007.
[11]Synopsys, TSuprem-4 Manual, 2007.
[12]Synopsys, Medici Manual, 2007.
[13]Everett J.P., Kearney M.J., Rueda H.A. , Johnson E.M., Aaen P.H. , Wood J. et al.,“Fast physical models for Si LDMOS power transistor characterization”, Microwave Symposium Digest (MTT), pp.1-4, 2011.
[14]林宸億,“傳統式LDMOSFET與Super junction LDMOSFET元件模型之建立”,華梵大學,2006。
[15]吳秀龍、陳軍甯、柯導明、孟堅,“高壓LDMOS功耗的分析與設計” ,安徽大學電子科學與技術學院,2010。
[16]吳承炎,“高壓32V,0.13微米元件模擬與設計”,亞洲大學,2009。
[17]呂國培,“LDMOS 功率電晶體元件設計、特性分析及其模型之建立”,國立中央大學,2001。
[18]古美良,“SOI技術及其發展和應用”,壓電與聲光,Vol.28,P.236-239,2006。
[19]陳啟文,“絕緣層上的矽分析及應用” ,明新學報,Vol.32,P.103-115,2006。
[20]鄭晃忠、劉傳璽,“新世代積體電路製程技術”,東華書局,2011。
[21]Shan Sun, Jiann-Shiun Yuan, Shen, Z.J., “Performance of Trench Power MOSFET With Strained Si/SiGe Multilayer Channel”, Electron Devices, Vol. 58, pp.1517-1522, 2011.
[22]Donald A. Neamen, “Fundamentals of Semiconductor Physics and Devices”, 2005.
[23]Privitera, V. , La Magna A. , Spinella, C. , Fortunato, G. , Mariucci, L. and Cuscuna, M. et al. ,“Integration of Melting Excimer Laser Annealing in Power MOS Technology”, Electron Devices, Vol. 54, pp.852-860, 2007.
[24]Youngmin Kim,“MOSFET Performance Degradation Induced by Trench Isolation Oxide Step”, Journal of Korean Physical Society, Vol. 42, No. 6, p.821-824 , 2003.
[25]Toshiyuki Oishi, Katsuomi Shiozawa, Akihiko Furukawa, Yuji Abe,and Yasunori Tokuda,“Isolation Edge Effect Depending on Gate Length of MOSFET's wth Various Isolation Structure”, IEEE Transactions on Electron Devices, Vol. 47, No. 4, p.822-827, 2000.
[26]C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Bianchi, R. Gwoziecki, S. Orain, E. Robilliart, C. Raynaud, and H. dansas,“Electrical Analysis of Mechanical Stress Induced by STI in Short MOSFETs Using Externally Appiled Stress”, IEEE Transactions on Electron Devices, Vol. 51, No. 8, p.1254-1261, 2004.
[27]Hyeokjae Lee, Jeong Mo Hwang, Young June Park, Hong Shick Min, “A Leakage Current Mechanism Caused by the Interaction of Residual Oxidation Stress and High-Energy Ion Implantation Impact in Advanced CMOS Technology”, IEEE Electron Device Letters, Vol.20, No. 5, p.251-253, 1999.
[28]林鴻志,“奈米金氧半電晶體元件技術發展趨勢 (I)”,奈米通訊第七卷第一期,2000。
[29]Peter Smeys, “Local Oxidation of Silicon for Insulation”, Chapter 2, Ph. D Thesis, Stanford University, p.13, 1996.
[30]Sung, J.M., Lu, C.Y., Fritzinger, L.B., Sheng, T.T., Lee, K.H., “Reverse L-shape sealed poly-buffer LOCOS technology”, Electron Device Letters, Vol. 11, pp.549-551, 1990.
[31]Miyamoto M. , Ohta H. , Kumagai Y. , Sonobe Y. , Ishibashi K. , Tainaka Y. ,“Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics”, Electron Devices, Vol. 51, pp.440-443, 2004.
[32]Joo-Hyoung Lee, Sung-Hyung Park, Key-Min Lee, Ki-Seok Youn,Young-Jin Park, Chel-Jong Choi, Tae-Yeon Seong, Hi-Deok Lee, “AStudy of Stress-Induced p+/n Salicided Junction Leakage Failure and Optimized Process Conditions for Sub-0.15 μm CMOS Technology”, IEEE Transactions on Electron Devices, Vol. 49, No. 11,p.1985-1992 , 2002.
[33]A. Steegen, A. Lauwers, M. de Potter, G. Badenes, R. Rooyackers, and K. Maex.,“Silicide and Shallow Trench Isolation Line Width Dependent Stress-Induced Junction Leakage”, VLSI Tech Dig.,p.180-181, 2000.
[34]Shimamoto S. , Yanagida Y., Shirakawa S. , Miyakoshi K. , Imai T. , Oshima, T. et al., “High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology”, Power Semiconductor Devices and ICs (ISPSD), pp.44-47, 2011.
[35]Meng Jian; Gao Shan; Chen Junning; Ke Daoming; Sun Weifeng; Shi Longxing; and Xu Chao, “An Analytical Model of a LDMOS On-Resistance Using a Well as a High Resistance Drift Region”, Chinese Journal of Semiconductors, Vol. 26,Page:1983-1988,2005.
[36]E.H. Stupp; S. Colak; and J. Ni,“Low specific on-resistance 400v LDMOST”, Electron Devices Meeting, Vol. 27,Page:426 – 428,1981.

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