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研究生:楊岱軒
研究生(外文):Tai-Hsuan Yang
論文名稱:應用於LTE系統之低功耗CMOS接收機射頻前端電路
論文名稱(外文):A Low Power CMOS RF Front-End Design for 4G LTE Application
指導教授:林光浩林光浩引用關係
指導教授(外文):Kuang-Hao Lin
學位類別:碩士
校院名稱:國立勤益科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:54
中文關鍵詞:低功耗接收機前端電路LTE
外文關鍵詞:Low powerReceiver front-endLTE
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本論文提出應用於LTE系統之低功耗CMOS射頻前端電路,符合3GPP LTE之系統規範,並採用低中頻接收機架構,其中包含了一差動式源極衰減低雜訊放大器與摺疊式混頻器。由於LTE是一應用於手持式裝置的通訊協定,因此在設計電路時以低功率消耗為訴求,本論文將低雜訊放大器之電晶體設計於次臨界導通區域,在不犧牲增益的情況下可有效減少偏壓電流,使整體功率消耗降低。使用PCSNIM(Power-constrained Simultaneous noise and input matching)之技術,可以提高電感衰減式共源極低雜訊放大器輸入阻抗匹配的設計彈性,在低功率的情形下,使其仍然有良好的雜訊表現。採用摺疊式混頻器的好處是能夠使用閃爍雜訊較低的PMOS原件來組成開關級的設計,如此可進一步減少輸出端之雜訊。本論文中之電路設計是以TSMC 0.18μm CMOS製成進行模擬,並透過CIC申請下線,完成晶片製作。本電路操作於1.2V電壓下,消耗電流為2.27mA,增益為12.52dB,P1dB為−9dBm,IIP3為−4 dBm,雜訊指數為18.31dB。
The thesis develop a 2.6-GHz receiver RF front-end for 3GPP LTE system. Low-IF technique has been chosen as the receiver architecture. The RF front-end includes differential source inductor degeneration LNA and folded-cascode mixer.
Due to the LTE system is applied to portable device, to achieve low power consumption issue, all of the LNA transistors are biased in subthreshold region, which can offer superior gain per current consumption. With power-constrained simultaneous noise and input matching (PCSNIM) technique, the input matching design of LNA become more flexible and still have good noise performance at low power consumption situation. One of advantages of folded-cascode mixer is implemented using PMOS device as switching stage for lower flicker noise than NMOS. Another advantage is that the LNA stage and the switching stage are separated in DC biasing such as the switching stage can operates in much lower dc current as compared to the LNA stage for less noise contributed at output. The circuit operated under a supply voltage of 1.2 V and current consumption of 2.27 mA. According to measurement results, the RF front-end achieves 12 dB conversion gain with P1dB of −9 dBm and noise figure of 18.31 dB. IIP3 is −4.04 dBm.
The design of these circuits is based on the TSMC 0.18μm CMOS process. This chip has been fabricated by the support of National Chip Implementation Center in Taiwan.
致 謝 i
摘 要 ii
Abstract iii
目 錄 iv
圖 目 錄 vii
表 目 錄 x
第一章 緒論 1
1.1 前言 1
1.2 低功率消耗設計動機 3
1.3 論文組織 3
第二章 4G系統規範與射頻接收機架構 5
2.1 4G系統簡介 5
2.1.1 WiMAX系統 6
2.1.2 LTE系統 7
2.2 LTE射頻參數與規格 9
2.2.1 雜訊指數 9
2.2.2 非線性特性 10
2.3 射頻接收機架構簡介 13
2.3.1 正交超外差接收機 13
2.3.2 直接降頻接收機 14
2.3.3 低中頻接收機 15
2.3.4 應用於LTE系統之數位低中頻接收機 17
第三章 射頻CMOS主動電路分析與設計 18
3.1 線性度與雜訊指數之設計分析 18
3.2 CMOS 低雜訊放大器原理分析 19
3.2.1 電阻終端式低雜訊放大器 20
3.2.2 並串聯回授式低雜訊放大器 20
3.2.3 1/gm終端式低雜訊放大器 21
3.2.4 電感衰減式低雜訊放大器 22
3.3 CMOS 混頻器原理分析 25
3.3.1 單平衡式混頻器 26
3.3.2 雙平衡式混頻器 28
3.4 應用於LTE系統之低功耗CMOS射頻前端電路設計 29
3.4.1 傳統CMOS射頻接收機電路 30
3.4.2 改良型CMOS射頻接收機電路 31
3.5 CMOS射頻機體電路設計流程與模擬結果 37
3.5.1 射頻積體電路設計流程 37
3.5.2 LTE系統之低功耗CMOS射頻前端電路模擬結果 38
第四章 量測環境設置與實驗結果 43
4.1 電路量測環境設置 43
4.2 電路實際量測結果 46
第五章 結論 52
參考文獻 53
[1] LTE Connected Car: mobile broadband, on wheels, http://www2.alcatel- lucent.com/blogs/corporate/2009/11/lte-connected-car-mobile-broadband-on-wheels/
[2] GSA- Global mobile Suppliers Association, http://www.gsacom.com/
[3] Aaron Carroll and Gernot Heiser, “An Analysis of Power Consumption in a Smartphone,” USENIX Annual Technical Conference, June. 2010.
[4] 3G vs 4G, http://www.diffen.com/difference/3G_vs_4G
[5] MAN, http://en.wikipedia.org/wiki/Metropolitan_area_network
[6] 3GPP TS 36.101, http://www.3gpp.org/ftp/specs/html-info/36101.htm
[7] LTE System Development in Taiwan (台灣發展LTE系統瓶頸與問題), https://sites.google.com/site/changch1011/my-blog/LTE-System-Development-in-Taiwan
[8] B. Razavi, RF Microelectronics, 2ed Edition, Prentice Hall, 2011.
[9] CIC, Design of RF CMOS IC Training Manual, Jan. 2012.
[10] Hoai-Nam Nguyen, Viet-Hoang Le, Ki-Uk Gwak, Jeong-Yeol Bae, Seok-Kyun Han and Sang-Gug Lee, “Low power, high linearity wideband receiver front-end for LTE application,” Advanced Communication Technology (ICACT), 2011 13th International Conference on, pp. 640-643, Feb. 2011.
[11] 張盛富, 張嘉展, “無線通訊之射頻晶片模組設計”, 全華科技圖書, 2007
[12] T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press 2003.
[13] Trung-Kien Nguyen, Chung-Hwan Kim, Gook-Ju Ihm, Moon-Su Yang, and Sang-Gug Lee, “CMOS low-noise amplifier design optimization techniques,” IEEE Transaction on Microwave Theory and Techniques, Vol. 52, pp. 1433-1442. May. 2004.
[14] E. Seevinck, E. A. Vittoz, M. Plessis, T. H. Joubert, and W. Beetge, “CMOS translinear circuits for minimum supply voltage,” IEEE Trans. Circuits Syst. II: Analog Digit. Signal Processing, vol. 47, no. 12, pp. 1560-1564, Dec. 2000.
[15] Advanced Design System (ADS), http://www.home.agilent.com/en/pc-1297113/advanced-design-system-ads
[16] Cadence Custom IC Design, http://www.cadence.com/products/cic/pages/default.aspx
[17] W. B. Lin, D. Y. Jie, Z. X. Xing and L. Y. Jie, “A 2.4-GHz low-IF front-end receiver in 0.18-µm CMOS for IEEE 802.15.4 WPAN applications,” in Proc. IEEE ASIC, 2009, pp. 1137-1140.
[18] H. S. Jhon, I. Song, I. M. Kang and H. Shin, “2.4 GHz ISMband receiver design in a 0.18 µm mixed signal CMOS process,” IEEE Microwave and Wireless Components Letters., vol. 17, Oct. 2007, pp.736-738.
[19] Ro-Min Weng, Jing-Chyi Wang, and Hung-Che Wei, “A 1V 2.4GHz Down Conversion Folded Mixer,” in IEEE Asia Pacific Conference, Dec. 2006, pp. 1450-1452.
[20] E.-P. Hong, Y.-S. Hwang, and H.-J. Yoo, “Direct conversion RF front-end with a low power consumption technique for 2.4GHz ISM band,” in Special Issue on Asia Pacific Microwave Conference, Dec. 2007, pp. 898-903.
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