(18.206.187.91) 您好!臺灣時間:2021/05/19 01:17
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果

詳目顯示:::

: 
twitterline
研究生:吳昇峻
研究生(外文):Sheng-Jyun Wu
論文名稱:低溫製程氧化鋅薄膜電晶體及自組裝奈米金電荷捕捉層應用於快閃記憶體與熱處理電性之改善
論文名稱(外文):Low-Temperature Zinc Oxide Thin Film Transistors with Direct Assembly of Gold Nano-particles Charge Trapping Layer with Thermal Annealing for Improving Nonvolatile Memory Applications
指導教授:游信強游信強引用關係
指導教授(外文):Hsin-Chiang You
學位類別:碩士
校院名稱:國立勤益科技大學
系所名稱:電子工程系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:89
中文關鍵詞:奈米金奈米金連結層穿隧氧化層快閃記憶體記憶窗口元件可靠度
外文關鍵詞:Gold-nanoparticlesLinkerTunneling Oxide LayerFlash memoryMemory WindowReliability
相關次數:
  • 被引用被引用:0
  • 點閱點閱:121
  • 評分評分:
  • 下載下載:2
  • 收藏至我的研究室書目清單書目收藏:0
本論文的研究目的為以奈米金用自組裝的方法做為電荷捕捉層,並以低溫製程氧化鋅做為電晶體通道層,我們使用了APTMS、MPTES兩種不同的連結層來附著上我們的奈米金,再以原子力顯微鏡掃描元件的奈米金附著情況,再調整阻擋氧化層及穿隧氧化層的厚度,利用延續研究的溶膠凝膠法氧化鋅溶液作為通道層,完成以後元件擁有優良的寫入特性,其中又以APTMS的連結層,記憶視窗可以達到8伏特,證明了奈米金作為電荷捕捉層的記憶體元件是可行的,在最後,我們利用加熱的方式,使得放置一年後的元件,電性有相當不錯的改善。
This work reports a versatile technique for enhancing charge storage nonvolatile memory device using a direct assembly of gold-nanoparticles (AuNPs) as a charge trapping layer and zinc oxide (ZnO) as semiconductor layer. We have used two types of linker to deposit AuNPs, which are 3-aminopropyltrimethoxysilane (APTMS) and 3-mercaptopropyltriethoxysilane (MPTES) followed by gold colloidal. Atomic force microscopy (AFM) image showed the surface morphology of the well-separated immobilized AuNPs on a SiO2/p-Si. According to the programming operations, the memory device showed good programmable memory characteristics with 8 V memory windows with better characteristics, at last, thermal annealing for improving nonvolatile memory has been research.
Abstract (Chinese) I
Abstract (English) II
Acknowledgements (in Chinese) IV
Contents V
List of Tables VIII
List of Figures IX

Chapter 1: Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Thesis Organization 3

Chapter 2: Principles and Operations 4
2.1 Introduction of ZnO 4
2.1.1 ZnO Characteristics 4
2.1.2 Introduction of ZnO Oxygen Vacancy 8
2.1.3 Introduction of ZnO Deposition Method 9
2.1.4 ZnO Hot Anneal Treatment 12
2.2 Introduction of Thin Film Transistor 13
2.2.1 Structure of Bottom Gate Thin Film Transistor 13
2.2.2 Determination of the Threshold Voltage 13
2.2.3 Determination of the Field Effect Mobility 14
2.2.4 Determination of the On-Off Current Ratio 15
2.2.5 Polyimide Thin Film Transistor 15
2.3 Introduction of Flash Memory 17
2.3.1 Memory History 17
2.3.2 Structure of Flash Memory 20
2.3.3 Flash Memory Mechanism 27

Chapter 3: Fabrication of Gold Nano-particles Charge Trapping Layer Flash Memory 28
3.1 Introduction 28
3.2 Experimental 29
3.2.1 Experimental Equipment 29
3.2.2 Experimental Materials 33 3.2.3 Experimental Method 41
3.3 Results and Discussion 46
3.3.1 AFM Analysis of Gold nanoparticles 46
3.3.2 Mechanism 54
3.3.3 The C-V curve in the Gold-nanoparticles capacitor 56
3.3.4 I-V Characteristics 57
3.4 Summary 60

Chapter 4: Thermal Annealing for Improved Nonvolatile Memory Reliability Applications 62
4.1 Introduction 62
4.2 Results and Discussion 63
4.2.1 Thermal annealing for improved memory reliability 63
4.2.2 Thermal annealing for improved program properties 66
4.3 Summary 77

Chapter 5: Conclusions and Future Work 78
5.1 Conclusions 78
5.2 Future work 79

References 83

[1] Yujeong Seo, Min Yeong Song, Ho-Myoung An, and Tae Geun Kim, “A CMOS-Process-Compatible ZnO-Based Charge-Trap Flash Memory”, IEEE Electron Device Lett., Vol. 34, No. 2, 2013.
[2] Tsung-Yu Chiang, William Cheng-Yu Ma, Yi-Hong Wu, Kuan-Ti Wang, and Tien-Sheng Chao, “A Novel p-n-Diode Structure of SONOS-Type TFT NVM With Embedded Silicon Nanocrystals”, IEEE Electron Device Lett., Vol. 31, No. 11, 2010.
[3] Yuan-Feng Chen, Jeng Gong, Wei-Jen Tung, Shang-Wei Chou, and Erik S. Jeng, “Characteristics of n-Channel MOSFETs With Tailored Source/Drain Extension for Mask ROM and EEPROM Applications”, IEEE Trans. Electron Devices, Vol. 56, No. 9, 2009.
[4] By Jang-Sik Lee, Yong-Mu Kim, Jeong-Hwa Kwon, Hyunjung Shin, Byeong-HyeokSohn, and Jaegab Lee, “Tunable Memory Characteristics of Nanostructured, Nonvolatile Charge Trap Memory Devices Based on a Binary Mixture of Metal Nanoparticles as a Charge Trapping Layer”, Adv. Mater. 21, 178–183, 2009.
[5] Soo-Jin Kim, Young-Su Park, Si-Hoon Lyu, and Jang-Sik Lee, “Nonvolatile nano-floating gate memory devices based on pentacene semiconductors and organic tunneling insulator layers”, Appl. Phys. Lett., 96, 033302, 2010.
[6] Su-Ting Han, Ye Zhou, Zong-Xiang Xu, Long-Biao Huang, Xiong-Bo Yang, and V. A. L. Roy, “Microcontact Printing of Ultrahigh Density Gold Nano-particle Monolayer for Flexible Flash Memories”, Adv. Mater. 24, 3556–3561, 2012.
[7] Hyun-woo Park, Kwun-Bum Chung, Jin-Seong Park, “A role of oxygen vacancy on annealed ZnO film in the hydrogen atmosphere”, Current Applied Physics, S164-S167, 2012.
[8] S. J. Pearton, D. P. Norton, K. I. , Y. W. Heo and T. Steiner, “Recent progress in processing and properties of ZnO”, Progress in Materials Science, vol. 50, pp. 293-340, 2005.
[9] N. Y. Yuan, S. Y. Wang, C. B. Tan, X. Q. Wang, G. G. Chen, J. N. Ding, “The influence of deposition temperature on growth mode, optical and mechanical properties of ZnO films prepared by the ALD method”, Journal of Crystal Growth, 366, 43–46, 2013.
[10] V. Craciun, J. Elders, J. G. E. Gardeniers, and Ian W. Boyd, “Characteristics of high quality ZnO thin films deposited by pulsed laser deposition”, Appl. Phys. Lett. 65 (23), 1994.
[11] Nick M. Sbrockey, Joseph D. Cuchiaro, Brent H. Hoerman, L. GaryProvost, Catherine E. Rice, Shangzhu Sun and Gary S. Tompa, “ZnO thin films by MOCVD”, The Advanced Semiconductor Magazine, Vol. 17, No. 7, 2004.
[12] Yumi Kawamura, Masahiro Horita, and YukiharuUraoka, “Effect of Post-Thermal Annealing of Thin-Film Transistors with ZnO Channel Layer Fabricated by Atomic Layer Deposition”, Japanese Journal of Applied Physics 49, 2010.
[13] Ju Ho Lee, Cheol Hyoun Ahnb, Sooyeon Hwang, Chang Ho Woo, Jin-Seong Park, HyungKoun Cho, Jeong Yong Lee, “Role of the crystallinity of ZnO films in the electrical properties of bottom-gate thin film transistors”, Thin Solid Films, 519, 6801–6805, 2011.

[14] Yung-HaoLina, Hsin-Ying Lee, Ching-Ting Leea, Cheng-Hsu Chou, “Mechanisms of ZnO buffer layer in bottom gate ZnO: Al transparent thin film transistors”, Materials Chemistry and Physics, 134, 2012.
[15] H. Kavak, H. Shanks, “Stability of hydrogenated amorphous silicon thin film transistors on polyimide substrates”, Solid State Electron., 2005.
[16] C. S. Yang, L. L. Smith, C. B. Arthur, G. N. Parsons, “Stability of low-temperature amorphous silicon thin film transistors formed on glass and transparent plastic substrates”, J. Vac. Sci. Technol. B. 18, 2000.
[17] K. Long, A. Z. Kattamis, I. C. Cheng, H. Gleskova, S. Wagner, J. C. Sturm, “Stability of amorphous silicon TFTs deposited on clear plastic substrates at 250℃ to 280℃”, IEEE Electron Device Lett. 27, 2006 .
[18] K. S. Girotra, J. H. Souk, K. Chung, S. Lim, S. Kim, B. J. Kim, S. H. Yang, B. Choi, J. Goh, Y.R. Song, Y.M. Choi, “A 14.1 inch AMOLED Display Using Highly Stable PECVD Based Microcrystalline Silicon TFT Backplane”, SID Dig, pp. 1972-1975, 2006.
[19] T. Arai, N. Morosawa, Y. Hiromasu, K. Hidaka, T. Nakayama, A. Makita, M. Toyota, N. Hayashi, Y. Yoshimura, A. Sato, K. Namekawa, Y. Inagaki, N. Umezu, K. Tatsuki, “Micro Silicon Technology for Active Matrix OLED Display”, SID Dig, pp. 1370-1373, 2007.

[20] J. J. Huang, M. H. Lee, C. J. Tsai, Y. H. Yeh, “Hydrogenated amorphous silicon TFT fabricated on glass and polyimide substrate at 200℃”, Jpn. J. Appl. Phys. 46, 1295-1298, 2007.
[21] L. Guo, R. Lin, “Studies on the formation of microcrystalline silicon with PECVD under low and high working pressure”, Thin Solid Films 376, 249-254, 2000.
[22] K. S. Girotra, Y. M. Choi, B. J. Kim, Y. R. Song, B. Choi, S. H. Yang, S. Kim, S. Lim, “PECVD-based nanocrystalline-silicon TFT backplanes for large-sized AMOLED displays”, J. Soc. Inf. Disp. 15, 113-118, 2007.
[23] Y. H. Peng, C. H. Chen, C. C. Chang, Y. S. Lee, T. S. Huang, C. Y. Hou, K. F. Huang, Y. Y. Tseng, “32-Inch LCD TV Using Conventional PECVD Microcrystalline Silicon TFTs”, SID Dig, pp. 333-336, 2008.
[24] K. E., K. R. Cho, “Memristor MOS Content Addressable Memory For Future High Performance Search Engines”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010.
[25] Feyza B. Oruç, Furkan Cimen, Ayman Rizk, Mohammad Ghaffari, Ammar Nayfeh, “Thin-Film ZnO Charge-Trapping Memory Cell Grown in a Single ALD Step”, IEEE Electron Device Letters, Vol. 33, No. 12, 2012.
[26] Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, “Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage layer”, IEEE Trans. Electron Devices, Vol. 51, No. 7, pp. 1143–1147, 2004.

[27] Y. N. Tan, W. K. Chim, W. K. Choi, M. S. Joo, T. H. Ng, and B. J. Cho, “High-k HfAlO charge trapping layer in SONOS-type nonvolatile memory device for high speed operation” , in IEDM Tech. Dig., pp. 889–892, 2004.
[28] T. Sugizaki, M. Kohayashi, M. Ishidao, H. Minakata, M. Yamaguchi, Y. Tamura, Y. Sugiyama, T. Nakanishi, and H. Tanaka, “Novel multi-bit SONOS type flash memory using a high-k charge trapping layer” , in VLSI Symp. Tech. Dig., 2003.
[29] B. D. Salvo, C. Gerardi, R. van Schaijk, S. A. Lombardo, D. Corso, C. Plantamura, S. Serafino, G. Ammendola, M. van Duuren, P. Goarin, W. Y. Mei, K. van der Jeugd, T. Baron, M. Gely, P. Mur, and S.Deleonibus, “Performance and reliability features of advanced nonvolatile memories based on discrete traps” , IEEE Trans. Device Mater. Rel., Vol. 4, No. 3, pp. 377–389, Sep. 2004.
[30] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS”, IEEE Circuits Devices, Vol. 16, No. 4, pp. 22–31, Jul. 2000.
[31] Lee Chang Hyun, Choi Kyung In, Cho Myoung Kwan, Song Yun Heub, Park KyuCharn, Kim Kinam.“A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-gigabit Flash memories”, Electron Device Meeting, IEEE International, IEDM Technical Digest, p. 26.5.1–4, 2003.
[32] Park Youngwoo, Choi Jungdal, Kang Changseok, Lee Changhyun, Shin Yuchoel, Choi Bonghyn, et al, “Highly manufacturable 32 GB multi-level NAND Flash memory with 0.0098 l m2 cell size using TANOS cell technology”, IEEE International, Electron Devices Meeting. IEDM, p. 1–4, 2006.
[33] SeoJihyun, SeoJihyun, Lee Youngbok, Park Sungkee, LeemJongsoon, Kim Jaeseok, et al. “A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies”, Electron Devices Meeting, IEDM. IEEE International; p. 9.1.1–4, 2011.
[34] J. G. Park, J. S. Oh, S. D Yang, K. S. Jeong, Y. M. Kim, H. J. Yun, H. D. Lee and G. W. Lee, “Improvement of Reliability Characteristics using the N2 Implantation in SOHOS Flash Memory”, IEEE Nanotechnology Materials and Devices Conference, 2010.
[35] Y. B. Park, D. K. Schroeder., “Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM”, IEEE Trans. Electron Devices, Vol. 45, #6, pp. 1361-1368, 1998.
[36] J-D. Lee, J-H. Choi, D. Park, and K. Kim, “Effects of interface trap generation and annihilation on the data retention characteristics of Flash memory cells”, IEEE Trans. Device and Mater. Reliability, Vol. 4, #1, pp. 110-117, 2004.
[37] A. N. Shipway, M. Lahav, I. Willner, “Nanostructured Gold Colloid Electrodes”, Adv. Mater. Vol. 12, pp. 993, 2000.
[38] M. Valden, X. Lai, D. W. Goodman, “Onset of catalytic activity of gold clusters on titania with the appearance of nonmetallic properties”, Science Vol. 281, pp. 1647, 1998.
[39] M. D. Musick, C. D. Keating, M. Keefe, M. J. Natan, “Stepwise construction of conductive Au colloid multilayers from solution”, Chem. Mater. Vol. 9, pp. 1499, 1997.

[40] T. Ji, V. G. Lirtsman, Y. Avny, D. Davidov, “Preparation, Characterization, and Application of Au-Shell/Polystyrene Beads and Au-Shell/Magnetic Beads”, Adv. Mater. 13, 1253, 2001.
[41] J. Schmitt, G. Decher, W. J. Dressick, S. L. Brandow, R. E. Geer, R. Shashidhar, J. M. Calvert, “Metal nanoparticle/polymer superlattice films: Fabrication and control of layer structure”, Adv. Mater., Vol. 9, pp. 61, 1997.
[42] T. Ung, L. M. Liz-Marzan, P. Mulvaney, “Optical Properties of Thin Films of Au@SiO2 Particles”, J. Phys. Chem., Vol. 105, pp. 3441, 2001.

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊