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研究生:吳英志
研究生(外文):Ying-ChihWu
論文名稱:減少草稿式記憶體競爭之線上多核心排程器設計
論文名稱(外文):Design of an On-line Multicore Task Scheduler for Reducing Scratchpad Memory Contention
指導教授:張大緯
指導教授(外文):Da-Wei Chang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:資訊工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:41
中文關鍵詞:多核心系統單晶片草稿式記憶體排程演算法
外文關鍵詞:MPSoCSPMscheduling algorithm
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現今行動裝置如智慧型手機已越來越流行,這些設備甚至會使用多核心環境。然而,由於只能提供有限的電力供應,在這些設備上使用多核心環境會使得電力消耗問題變得更加嚴峻。因此,草稿式記憶體將有很大的潛力應用在此類設備上,因其電量消耗低於快取記憶體。但由於草稿式記憶體資源有限,且其會同時被多核心上的每個核心使用,因而產生了草稿式記憶體資源競爭的問題。在本篇論文中,我們提出線上排程演算法,欲藉此減低資源競爭問題。其作法為錯開對草稿式記憶體需求較大的程式使用核心的時間。由於我們希望此排程演算法能夠應用在多工系統上,而在此類系統上無法使用非線上演算法,故我們提出的排程演算法為線上執行;而根據我們的調查,本篇論文為第一個提出在應用草稿式記憶體的環境上的線上排程演算法。最後的實驗結果證實我們的演算法能夠確實減少在系統上各個程式的平均執行時間。
The portable devices like smart phone become more and more prevalent at present. The producers even employ MPSoC in their products, but the problem of power consumption also becomes more severe. Therefore, the SPM has more chance to be employed as the on-chip memory in these devices for the less power consumption than cache. However, like cache, the SPM space is limited and shared by each core in MPSoC, so the contention of SPM resource becomes an important problem. In this paper, we propose an on-line scheduling algorithm to solve the problem of SPM resource contention by avoiding the tasks which require large SPM space run simultaneously. As our survey, we are the first one that proposes an on-line scheduling in the SPM environment with dynamic tasks set. In the environment with dynamic tasks set, the off-line scheduler cannot work because what tasks will run cannot be known at compiler time. We use the trace-driven simulator to do our experiments, and as the result of our experiments, our scheduler can actually reduce the average execution time of the tasks in the system.
摘要 i
Abstract ii
誌謝 iii
Content iv
List of Tables vi
List of Figures vii
Chapter 1 Introduction 1
Chapter 2 Background 3
2.1 Hardware Architecture 3
2.2 Software Management 5
2.3 Motivation 6
Chapter 3 Related Works 8
3.1 SPM Allocation 8
3.2 Off-line SPM Scheduler 8
3.3 On-line Cache Scheduler 9
Chapter 4 Design and Implementation 11
4.1 Design Overview of SCAS 11
4.2 Task Profiling 13
4.3 Space Requirement Estimator 14
4.3.1. Computing Performance Improvement 14
4.3.2. Estimating SPM Space Requirements 15
4.4 Task Scheduling 20
Chapter 5 Evaluation 22
5.1 Experiments Setting 22
5.1.1 SimpleScalar 22
5.1.2 SPMSim 23
5.1.3 Hardware Overhead 23
5.1.4 Control Groups 24
5.2 Benchmarks 25
5.2.1 Classification of Benchmarks 25
5.2.2 Combination of Benchmarks 26
5.3 Average Execution Time 27
5.4 Energy Consumption 30
5.5 Execution Time of Each Task 32
5.6 Performance with Various α and β 34
5.7 Fairness 36
Chapter 6 Conclusion and Future Work 38
Reference 39
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[2] M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown: ‘MiBench: A free, commercially representative embedded benchmark suite’. WWC '01 Proceedings of the Workload Characterization, USA2001
[3] Todd Austin, Eric Larson, and Dan Ernst: ‘SimpleScalar: An Infrastructure for Computer System Modeling’. Computing & Processing (Hardware/Software), 2002
[4] Rajeshwari Banakar, Stefan Steinke, Bo-sik Lee, M. Balakrishnan, and Peter Marwedel: ‘Scratchpad Memory: A Design Alternative for Cache On-chip memory in Embedded Systems’. In Tenth International Symposium on Hardware/Software Codesign (CODES), 2002
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[6] Vivy Suhendra, Chandrashekar Raghavan, and Tulika Mitra: ‘Integrated Scratchpad Memory Optimization and Task Scheduling for MPSoC Architectures’. CASES '06 Proceedings of the 2006 international conference on Compilers, Architecture and Synthesis for Embedded Systems, USA2006
[7] Robert Pyka, Christoph Faßbach, Manish Verma, Heiko Falk, and Peter Marwedel: ‘Operating system integrated energy aware scratchpad allocation strategies for multiprocess applications’. SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems, USA2007
[8] Muralimanohar Naveen, Balasubramonian Rajeev, Jouppi Norman P.: ‘CACTI 6.0: A Tool to Model Large Caches’. International Symposium on Microarchitecture, 2007
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[10] Andreas Merkel, and Frank Bellosa: ‘Memory-aware Scheduling for Energy Efficiency on Multicore Processors’. HotPower'08 Proceedings of the 2008 Conference on Power Aware Computing and Systems, USA2008
[11] Satoshi Yamada, and Shigeru Kusakabe: ‘Impact of priority bonuses of Inter-Core Aggregation Scheduler on a commodity CMP platform’. Workshop on Managed Many-Core Systems, USA2009
[12] Lei Zhang, Meikang Qiu, Wei-Che Tseng, and Edwin H.-M. Sha: ‘Variable Partitioning and Scheduling for MPSoC with Virtually Shared Scratch Pad Memory’. Journal of Signal Processing Systems archive, Volume 58 Issue 2, Feb 2010
[13] Yunlian Jiang, Kai Tian, and Xipeng Shen: ‘Combining Locality Analysis with Online Proactive Job Co-Scheduling in Chip Multiprocessors’. HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers, Berlin2010
[14] Bathen, L.A.D., Dutt, N.D., Dongyoun Shin, and Sung-Soo Lim: ‘SPMVisor: Dynamice ScratchPad Memory Virtualization for Secure, Low Power, and High Performance Distributed On-Chip Memories’. 2011 Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, USA2011
[15] Mrinmoy Ghosh, Ripal Nathuji, Min Lee, Karsten Schwan, and Hsien-Hsin S. Lee: ‘Symbiotic Scheduling for Shared Caches in MultiCore Systems Using Memory Footprint Signature’. ICPP '11 Proceedings of the 2011 International Conference on Parallel Processing, USA2011
[16] Yingxin Wang, Yan Cui, Pin Tao, Haining Fan, Yu Chen, and Yuanchun Shi : ‘Reducing Shared Cache Contention by Scheduling Order adjustment on Commodity Multi-Cores’. IPDPSW '11 Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum, USA2011
[17] Marongiu, and A., Benini, L.: ‘An OpenMP Compiler for Efficient Use of Distributed Scratchpad Memory in MPSoCs’. IEEE Transactions on Computers, 2012
[18] Ching-Lun Lin, Da-Wei Chang and Alvin W. Y. Su: ‘SPMSim: a Flexible Trace-Driven Simulator for MPSoC Using Scratchpad Memory’. The 23rd VLSI Design/Cad Symposium, Taiwan2012
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