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研究生:馮雅聖
研究生(外文):Ya-ShengFeng
論文名稱:元件尺寸對於N型橫向擴散金氧半電晶體特性及其可靠度之影響
論文名稱(外文):Effects of Device Dimension on Characteristics and Reliability of N-LDMOS Transistors
指導教授:陳志方
指導教授(外文):Jone-Fang Chen
學位類別:碩士
校院名稱:國立成功大學
系所名稱:微電子工程研究所碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:73
中文關鍵詞:熱載子克爾克效應高壓元件
外文關鍵詞:Hot carrierKirk effectHV device
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本篇論文主要目的是對不同元件尺寸具P型埋入層之n型通道橫向擴散金氧半場效電晶體之元件特性與熱載子可靠度,進行研究與探討。本論文所使用的元件主要有四個尺寸參數: b(累積區長度)、a(閘極控制的STI長度)、c(不受閘極控制的STI長度)、R(P型埋入層延伸進入累積區與STI交界之長度)。
對元件特性而言,累積區長度相較於閘極控制的STI長度與不受閘極控制的STI長度及P型埋入層延伸進入累積區與STI交界之長度影響較大。我們選擇了一個標準的元件尺寸,進行定電壓的熱載子stress實驗並討論熱載子退化現象與退化機制。藉由TCAD與Charge pumping分析,在不同stress條件下的退化機制可被較完整的討論,其中包含退化原因(接面陷阱Nit或電荷補陷Not)及退化位置。
元件尺寸對於熱載子可靠度的影響也在本篇論文被討論,由於元件常被使用在LED Boost電路上,操作上Vg電壓不常維持於高壓,因此stress電壓主要使用low Vg,而P型埋入層延伸進入累積區與STI交界之長度近年來只有少數文獻提及對元件特性之影響,缺乏熱載子可靠度的探討,因此本篇論文對於P型埋入層延伸進入累積區與STI交界之長度亦進行high Vg stress探討熱載子可靠度。
最後,我們可以對元件效能做一結論,在low Vg stress之下,所有尺寸的放大可以提高元件生命期且對導通電壓(Vt)不造成影響,但在high Vg stress之下,P型埋入層延伸進入累積區與STI交界之長度的放大,加強kirk effect而使元件生命期縮短。如要最有效的提高off breakdown電壓,縮短累積區長度為最佳選擇,但將會犧牲Ron與元件生命期。而提高閘極控制的STI長度、不受閘極控制的STI長度可提高off breakdown電壓與元件生命期,但犧牲Ron。延長P型埋入層延伸進入累積區與STI交界之長度在不影響Ron的情況下,又可提高off breakdown電壓及low Vg時的元件生命期,以上結論提供元件設計者做為參考,視元件使用條件選擇最適合的參數。

The main purpose of this thesis is to investigate the device characteristics and hot carrier reliability of P-buried N-type LDMOS with different device dimension. The device used in this thesis has four main layout parameters b, a, c, and R, which corresponds to the length of accumulation region, STI length with gate control, STI length without gate control, and the length of P-buried from the end of STI near accumulation region to drain side, respectively.
For device characteristics, the effect of b rule is more significant than a, c, and R rule. Then, we choose a standard device dimension to perform hot-carrier stressing experiment with constant voltage, and discuss the degradation and degradation mechanism induced by hot carrier. By the means of TCAD and charge pumping technique, the degradation mechanism under different stress condition could be verified completely, including the damage type (Nit or Not) and damage location.
The effect of dimensions on hot carrier reliability is also discussed in this thesis. The device used in this thesis is usually applied in LED boost circuit, the voltage of Vg is not operated on high Vg region, so the stress experiment is focused on low Vg. In addition, many papers mention its good characteristics of LDMOS with P-buried layer, lack of the investigation on hot carrier reliability. Thus, we also perform the high Vg stressing to check the effect of dimension R on hot carrier reliability.
Finally, we can summarize the device performance as the following. Under the low Vg stress condition, the extending of all dimensions (b, a, c, R) can increase the device lifetime and no impact on Vth. Under high Vg stress condition, the enhancement of Kirk effect induced by P-buried layer (R rule) cause the decrease of device lifetime. If we want to increase Vbd_dss more efficiently, the b rule is the best choice but sacrifice Ron and device lifetime. By increasing the length of a and c, Vbd_dss and device lifetime could be improved but sacrifice Ron. For R rule, Vbd_dss and lifetime at low Vg could be improved and no impact on Ron. Depend on the purpose of device, we should choose the suitable condition precisely.

摘要 …………………………………………………………………………I
Abstract ……………………………………………………III
誌謝 …………………………………………………………………………V
Contents ……………………………………………………VI
List of Tables ……………………………………………………VIII
Figure Captions ……………………………………………………IX
Chapter 1 Introduction............................1
1.1 Motivation of this thesis.................1
1.2 Introduction of hot carrier reliability...2
1.3 Introduction of kirk effect...............3
1.4 Charge pumping technique..................4
1.5 About this thesis.........................7
Chapter 2 Measurement Description of Device Characteristics…..........18
2.1 Introduction..............................18
2.2 Measurement Methodology...................18
2.2.1 Measurement setup.........................18
2.2.2 Id-Vd measurement.........................18
2.2.3 Id-Vg measurement.........................19
2.2.4 Breakdown voltage measurement.............20
2.3 Description of Device and electrical characteristics...21
2.3.1 Device description........................21
2.3.2 Effect of dimension on device characteristics..22
2.4 Summary...................................23
Chapter 3 Degradations and mechanisms with hot carrier stress.......34
3.1 Introduction..............................34
3.2 Experiment Methodology and Stress condition....34
3.3 Experiment results........................35
3.4 Charge pumping analysis...................37
3.4.1 Experiment setup..........................37
3.4.2 Experiment results and discussion.........37
3.5 Summary...................................38
Chapter 4 Effects of device dimension on hot carrier reliability.....51
4.1 Introduction..............................51
4.2 Experiment setup..........................51
4.3 Experiment results........................51
4.4 Effect of dimension (b, a, c, R) on lifetime....52
4.5 Degradation induced by kirk effect with various R..54
4.6 Performance with different device dimension....54
4.7 Summary...................................56
Chapter 5 Conclusion and Future Work..............69
5.1 Conclusion................................69
5.2 Future work...............................70
Reference.........................................71

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