臺灣博碩士論文加值系統

本論文研究有別於傳統太陽能製程方式，將使用離子佈植和背面蝕刻製程於P型單晶以及P型類單晶基板以製作均勻性射極之高效率太陽能電池。
在基板的選擇上，我們使用兩種基板分別是單晶以及具有成本效益的類單晶基板來製作高效率太陽能電池。由於類單晶晶片表面具有90%以上面積是屬於〈100〉晶向，所以選擇鹼蝕刻製程於這兩種不同基板上形成金字塔表面以增加光的吸收。有別於傳統熱磷擴散製程方式，我們使用離子佈植機在兩種晶片上佈植磷原子，接著我們使用熱氧化來活化磷原子，藉著改變氧化溫度為810˚C，840˚C，870 ˚C和900 ˚C找出最佳值並且和傳統熱擴散製程做比較。我們發現離子佈植製程於兩種不同基板上的片電阻會比熱磷擴散有較好的均勻度(〈3%)，同時我們使用少數載子壽命測量儀(WCT-120)，用來評估熱擴散以及熱氧化製程優劣，其結果顯示在兩種不同基板下，離子佈植製程的少數載子壽命以及implied VOC大於熱擴散製程。在pn製程接面形成後，有別於熱磷擴散製程，離子佈植製程後省略去除PSG層以及PN接面絕緣化兩道製程，接著用電漿輔助氣相沉積鍍上抗反射層以減少光反射，由於熱氧化製程會在晶片表面產生16.5 nm二氧化矽層，氮化矽的厚度必須修正，同時使用PC-1D模擬軟體來驗證此模型並找出氮化矽厚度的最佳值，其模擬結果和實際值結果類似，我們鍍上57 nm氮化矽於二氧化矽上，並利用分光光度計比較傳統製程的差異，在短波長波段300nm~400nm，離子佈植製程的會比傳統熱擴散來的差，在長波長波段800nm~1200nm，離子佈植製程的會比傳統熱擴散來的好，整體而言離子佈植的反射比傳統製程來的好。最後我們使用網印電極線製程在晶片正面網印銀漿料，背面焊接處網印銀漿料，背面其餘部分為鋁漿料。在I-V電性方面，使用離子佈植製程的效率優於傳統製程0.54%以及0.47%分別於單晶基板與類單晶基板上。接下來我們使用離子佈植製程和背面蝕刻方式於兩種基板上，在這裡我們使用四種不同蝕刻深度，分別為對照組0um以及實驗組3 µm±0.1 µm、6 µm±0.1 µm和9 µm±0.1 µm探討其影響。利用分光光度計以及反射加權指數(RW%)得知蝕刻深度越多情況下會在長波長波段(〉1100nm)反射越多光線，單晶RW%分別為為14.54%，14.71%，14.88%，14.95%。我們使用電子顯微鏡(SEM)分析不同蝕刻深度下BSF以及Al-Si 接面的變化，在兩種不同晶片上我們得到相同的結果，當蝕刻深度越深時(〉6um)，有比較平坦的BSF以及Al-Si 接面，這會減少背面不飽和鍵以及表面缺陷而增加少數載子壽命，我們使用量子響應量測儀來量測不同蝕刻深度下的表現，結果顯示在中長波段500nm-1200nm，蝕刻深度越深時(〉6um)內部量子響應較好，這是因為電池片有好的BSF以及Al-Si 層，在效率方面我們優於傳統製程0.84%以及0.74%分別於單晶基板與類單晶基板上，我們成功導入大量製程於這兩種基板上

The main goal of this dissertation is high efficiency blanket emitter Si Solar Cell fabricated on p-type mono and quasi-mono substrate by ion implantation and inline backside rounding process in contrast with conventional thermal POCl3 process.
We use two kinds of silicon substrate to be starting material for fabricating high efficiency solar cell. One is p-type monocrystalline and the other is cost-effective p-type quasi-mono. Because p-type quasi-mono have more than 90% area with 〈100〉 direction, both of these two wafers were performed alkaline texturing process to produce pyramids on the surface and absorb more incoming sunlight. Comparing with conventional thermal POCl3 process, an ion implanter machine is used to implant phosphorous atom on two kinds of substrate. After ion implantation process, thermal oxide annealing process is used to active phosphorous atom. There are 4 different peak temperature, 810, 840,870 and 900 degree performed to find out the best result in annealing step. Comparing with the conventional POCl3 process, uniformity of Rsheet in ion implant process is less than 3% which is better than POCl3 diffusion. We estimate the minority carrier lifetime and implied VOC by WCT-120 tool. The results show that we will get better minority carrier lifetime and implied VOC in implant process on two kinds of substrate. After PN junction formation, two process steps, phosphosilicate glass (PSG) removal and junction isolation process formed by conventional thermal POCl3 diffusion process were be eliminated in ion implant process flow. Anti-reflection coating layer is deposited on top of the SiO2 in order to minimize reflection by PECVD. According to thinner oxide 16.5nm appeared on the surface, the thickness of silicon nitride should be modulated. In order to validate the model, we figure out the optimization SiNx thickness by PC-1D simulation program and the simulation result is similar with the experimental result. Thickness 57nm SiNx was deposited on the SiO2 and compared the performance with the POCl3 process. In the short wavelength range 300nm~400nm, the reflection of implanter process is worse than POCl3 process. In the long wavelength range, the reflection of POCl3 process is worse than that of implant process. Generally, the reflection of the implant process is better than that of POCl3 process. Finally, Ag paste is printed on the front side surface and on the backside busbar by screen printing. Al paste is printing on the remaining backside area. The I-V data shows the efficiency of ion implant process is 0.54% and 0.47% higher than that of conventional process on monocrystalline and quasi-mono substrate. We implement ion implant and backside rounding process on these two substrates. There are four different etching depths used to estimate the performance in this study. The control group is 0 µm (without backside rounding process) and the experimental group is 3 µm±0.1 µm, 6 µm±0.1 µm, and 9 µm±0.1 µm. As the etching depth increases, the reflectivity increases at long wavelength (〉1000nm). The RW% on monocrystalline wafer after backside rounding process are 14.54%，14.71%，14.88% and 14.95%. We analyze BSF layer and Al-Si layer of different etching depth by scanning electron microscope (SEM). The result shows that as the etching depth gets higher (more than 6um), we will have the better uniformity of BSF and Al-Si layer. This will reduce the dangling bonds and surface defect states density, which will increase minority carrier lifetime. Quantum efficiency measurement is used to measure performance of different etching depth. The result shows that in the mid and long wavelength (500nm~1200nmn), quantum efficiencies will be better as the etching depth gets higher (more than 6um). This is due to better uniformity of BSF and Al-Si layer which is accordance with the result of SEM. The I-V data shows the efficiency of ion implant process is 0.84% and 0.74% higher than that of conventional process on monocrystalline and quasi-mono substrate. We put this technology into mass production on these two substrates successfully.

Abstract (in Chinese) --------------------------------------------------------------- I
Abstract (in English) -------------------------------------------------------------- III
Acknowledgement ----------------------------------------------------------------- VI
Contents ---------------------------------------------------------------------------- VII
Table Captions -----------------------------------------------------------------------X
Figures Captions -------------------------------------------------------------------XII
CHAPTER 1 Introduction --------------------------------------------------------- 1
1-1 Background and Motivation ---------------------------------------------------------- 1
1-2 Organization of dissertation ---------------------------------------------------------- 2
References------------------------------------------------------------------------- 4
CHAPTER 2 Experimental Equipment and Relevant Theory ------------- 6
2-1 Theory of solar cells ------------------------------------------------------------------ 6
2-1-1 Photovoltaic effect and basic solar cell parameters ----------------------------- 6
2-1-2 Diagram of solar cells ---------------------------------------------------------10
2-2 Junction Formation by Ion Implant ------------------------------------------------- 12
2-3 Experimental details and analytic --------------------------------------------------- 12
2-3-1. Scanning Electron Microscope ----------------------------------------------- 12
2-3-2. UV-Visible-NIR Spectrophotometers ---------------------------------------- 13
2-3-3. WCT-120 Lifetime Tester System -------------------------------------------- 13
2-3-4. I-V tester --------------------------------------------------------------------- 15
References---------------------------------------------------------------------------------17
CHAPTER 3 Silicon Solar Cells Fabricated by Ion Implantation Process on p-type Monocrystalline Substrates------------------------------------------ 28
3-1 Fabrication of Ion Implanted Blanket Emitter on Monocrystalline Substrates---------29 3-2 Characteristics of Ion Implanted Blanket Emitter on Monocrystalline Substrates---- 30
3-3 Summary --------------------------------------------------------------------------- 33
References---------------------------------------------------------------------------------35
CHAPTER 4 Silicon Solar Cells Fabricated by Ion Implantation Process on p-type Quasi-Mono Substrates----------------------------------------------- 46
4-1 Fabrication of Ion Implanted Blanket Emitter on Quasi-mono Substrates------------47
4-2 Characteristics of Ion Implanted Blanket Emitter on Quasi-mono Substrates-------- 50
4-3 Summary --------------------------------------------------------------------------- 54
References---------------------------------------------------------------------------------57
CHAPTER 5 Silicon Solar Cells Fabricated by Ion Implantation and Inline Backside Rounding on p-type Monocrystalline Substrates---------65
5-1. Fabrication of Ion Implanted Blanket Emitter and Backside Rounding on p-type Monocrystalline Substrates --------------------------------------------------------------66
5-2. Characteristics of Ion Implanted Blanket Emitter and Backside Rounding on p-type Monocrystalline Substrates ---------------------------------------------------- 69
5-3. Summary --------------------------------------------------------------------------- 72
References---------------------------------------------------------------------------------74
CHAPTER 6 Silicon Solar Cells Fabricated by Ion Implantation Process and Inline Backside Rounding on p-type Quasi-Mono Substrates------- 83
6-1. Fabrication of Ion Implanted Blanket Emitter and Backside Rounding on p-type Quasi-mono Substrates ----------------------------------------------------------------- 84
6-2. Characteristics of Ion Implanted Blanket Emitter and Backside Rounding on p-type Quasi-mono Substrates ----------------------------------------------------------------- 86
6-3. Summary ---------------------------------------------------------------------------90
References---------------------------------------------------------------------------------91
CHAPTER 7 Conclusion and Future Work --------------------------------- 101
7-1 Conclusion ------------------------------------------------------------------------ 101
7-2 Future Work ----------------------------------------------------------------------- 104
References--------------------------------------------------------------------------------106

Chapter 1
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[7] H.F. Wolf, Semiconductors, John Wiley ＆Sons.Inc (1971)
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[11] D. Redfield, “Method for evaluation of antireflection coatings, Solar Cells, vol. 3, pp. 27-33 (1981).
[12] R. Low, A. Gupta et al., “High Efficiency Selective Emitter Enabled through Patterned Ion Implantation, 35th IEEE PVSC, Honolulu (2010).
[13] J. Benick, et al., “Very Low Emitter Saturation Current Densities on Ion Implanted Boron Emitters, 25th EUPVSEC, Valencia, Spain (2010).
[14] T. Janssens, et al., “Implantation for an Excellent Definition of Doping Profiles in Si Solar Cells, 25th EUPVSEC, Valencia, Spain (2010).
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Chapter 5
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[15] S. M. Sze, Semiconductor Device Physics and Technology, John Wiley＆ Sons Inc., (1969).
[16] D. Redfield, “Method for evaluation of antireflection coatings, Solar Cells, vol. 3, pp. 27-33 (1981).
[17] G. E. Jellison, F. A. Modine, “Optical constants for silicon at 300 and 10 K determined from 1.64 to 4.73 eV by ellipsometry, Journal of Applied Physics, vol. 53, pp. 3745 (1982).
[18] Ed. Palik, Handbook of Optical Constants of Solids, Academic Press, New York (1985).

Chapter 6
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[4] P. J. Cousins, J. E. Cotter, Minimizing Lifetime Degradation with thermal Oxidation of upright randomly textured silicon surfaces, Solar Energy Materials and Solar Cells, 90, pp. 228-240 (2005)
[5] A.Müller, M.Gosh, R.Sonnenschein, P.Woditsch, Materials Science and Engineering B134, 257 (2006).
[6] N. Stoddard, B. Wu, I. Witting et al., Casting single crystal silicon: G. Rozgonyi, R. Clark, Casting single crystal silicon: Novel defect profiles from BP Solar's Mono2 wafers, Solid State Phenomena, vol. 131-133, pp. 1-8 (2008).
[7] H.F. Wolf ,Semiconductors,John Wiley ＆Sons.Inc (1971)
[8] A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley ＆ Sons Inc (1967)
[9] D. V. Morgan, K. Board, and R. H. Cockrum, An introduction to Microelectronic Technology, John Wiley ＆ Sons Inc (1985).
[10] S. M. Sze, Semiconductor Device Physics and Technology, John Wiley＆ Sons Inc., (1969).
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CHAPTER 7
[1] Minsung Jeon, Joonsung Lee, Hoon Oh, Jongkeun Lim, Myungik Hwang, Jaewon Seo, Sangkyun Kim, Wonjae Lee, Eunchol Cho, “Emitter Formation Using Ion Implatation Method For Fabrication Of Crystalline, 25th EUPVSEC, pp2438, (2010).
[2] S.W. Glunz, S. Rein, J.Y. Lee and W. Warta, Journal of Applied Physics 90 (2001) 2397.
[3] J. Renshaw, A. Rohatgi, 37th IEEE PVSC., (2011) 2924.