臺灣博碩士論文加值系統

本篇論文提出了一特殊應用晶片語者辨識系統架構，本架構共分三大模組，分別為：特徵擷取模組、訓練模組以及辨識模組。
特徵擷取模組採用線性預估係數(Linear Predictive Cepstral Coefficients)作為語者聲紋之特徵，在此模組中，我們設計一個可切換式蝴蝶狀的架構，並利用資料傳遞的重複性，使得此模組具有高通量的特性，另外，可切換式的設計，也可針對線性預估係數的某些運算作加速，且提高運算單元的使用率，有效的節省晶片面積，並提供良好的效能。訓練模組採用本實驗室開發之依序最佳化演算法之可重組式硬體架構，其平行式網狀的架構，可藉由改變運算單元間的資料傳遞路徑，來最佳化整體的效能及運算速度。辨識模組採用支援向量機的概念，以訓練後的分類平面作為分類依據，為二元分類器，但是為了達到多人分類的目標，本模組加入了投票機制的分析運算電路，可完成6人的語者辨識，使本晶片擁有更高的應用彈性，並且是目前第一顆完整的特殊應用晶片語者辨識系統。

This paper proposed an application-specific integrated circuit (ASIC) architecture for speaker recognition. There are three parts of this proposed system, which is including: feature extraction module, training module, and recognition module. LPCC (Linear Predictive Cepstral Coefficients) is adopted into the proposed feature extraction module. As the characteristics of symmetrical and periodical data transmission, we design a switchable butterfly architecture to optimize the efficiency of data accessing. Moreover, this module employs the reusable mechanism to perform two modes for achieving high speed and low chip area requirement. Reconfigurable hardware design for sequential minimal optimization (SMO) is applied in the proposed training module. Overall, this training module is a parallel-mesh architecture which contains 16 processing elements (PEs).We can switch the proposed training module into different mode by changing the datapath to speed up various training tasks. The last part of the proposed ASIC architecture is recognition module which is utilized Support Vector Machine (SVM) algorithm as classifier. For SVM, we design a voting analysis circuit so that we can achieve multi-class speaker recognition demand. The proposed design has been send to National Applied Research Laboratories (NAR Labs), and be manufactured by Taiwan Semiconductor Manufacturing Company Limited (TSMC).

摘要 IV
Abstract V
誌謝 VI
Contents VII
Table List IX
Figure List X
Chapter1 Introduction 1
1.1 Background 1
1.2 Related Work 1
1.3 Motivation 2
1.4 Thesis Organization 3
Chapter2 Speaker Recognition System Overview 5
2.1 System Overview of Speaker Recognition 5
2.2 Feature Extraction Algorithm 6
2.3 Training Algorithm 12
2.4 Recognition Algorithm 21
Chapter3 Speaker Recognition System Hardware Design 24
3.1 Top Level Architecture 24
3.1.1 Proposed System Flow 24
3.1.2 Operation Mode of Proposed System 24
3.1.3 Memory Requirement evaluation 26
3.1.4 Fixed-point Analysis 27
3.2 SMO Training Block 28
3.2.1 Overview of SMO Training Block 28
3.2.2 Processing Element 30
3.2.3 SMO Computing Unit 31
3.2.4 Distributed Memory 33
3.3 LPCC Feature Extraction Block 35
3.3.1 Overview of LPCC Feature Extraction Block 35
3.3.2 Controller Design 37
3.3.3 Multiply-Accumulate-Tree Mode 38
3.3.4 Butterfly-Architecture Mode 45
3.4 SVM Recognition Block 46
Chapter4 Speaker Recognition System Implementation 49
4.1 Cell-based Chip Implementation 49
4.2 Simulation Results 51
4.3 Measurement Consideration 59
Chapter5 Conclusion 61
5.1 Specification Comparison and Conclusion 61
5.2 Future Work 63
References 64

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