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[1]N. Lotze and Y. Manoli, A 62 mV 0.13 um CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic, IEEE Journal of Solid-State Circuits, vol. 47, pp. 47-60, 2012. [2]A. Wang and A. Chandrakasan, A 180-mV subthreshold FFT processor using a minimum energy design methodology, IEEE Journal of Solid-State Circuits, vol. 40, pp. 310-319, 2005. [3]J. Wei, L. Sheng, H. Weifeng, and M. Zhigang, A 230mV 8-bit sub-threshold microprocessor for wireless sensor network, in IEEE International Conference on VLSI and System-on-Chip, 2011, pp. 126-129. [4]B. H. Calhoun, A. Wang, N. Verma, and A. Chandrakasan, Sub-Threshold Design: The Challenges of Minimizing Circuit Energy, in Proceedings International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368. [5]N. Verma, J. Kwong, and A. P. Chandrakasan, Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits, IEEE Transactions on Electron Devices, vol. 55, pp. 163-174, 2008. [6]F. F. a. M. PEDRAM, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, IEICT TRANS. ELECTRON, vol. E88-C, 2005. [7]C. Jinhui, L. T. Clark, and C. Yu, Maximum - Ultra-low voltage circuit design in the presence of variations, Circuits and Devices Magazine, IEEE, vol. 21, pp. 12-20, 2006. [8]K. A. Bowman, S. G. Duvall, and J. D. Meindl, Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration, IEEE Journal of Solid-State Circuits, vol. 37, pp. 183-190, 2002. [9]A. R. Brown, G. Roy, and A. Asenov, Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture, IEEE Transactions on Electron Devices, vol. 54, pp. 3056-3063, 2007. [10]J. Kwong, Y. K. Ramadass, N. Verma, and A. P. Chandrakasan, A 65 nm Sub-Vt Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter, IEEE Journal of Solid-State Circuits, vol. 44, pp. 115-126, 2009. [11]M. Alioto, Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial, IEEE on Transactions Circuits and Systems I: Regular Papers, vol. 59, pp. 3-29, 2012. [12]N. Reynders and W. Dehaene, A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques, in Proc. IEEE Asian Solid State Circuits Conference, 2011, pp. 113-116. [13]H. Myeong-Eun, A. Raychowdhury, K. Keejong, and K. Roy, A 85mV 40nW Process-Tolerant Subthreshold 8x8 FIR Filter in 130nm Technology, in Proc. IEEE Symposium on VLSI Circuits, 2007, pp. 154-155. [14]H. Soeleman, K. Roy, and B. C. Paul, Robust subthreshold logic for ultra-low power operation, IEEE Transactions on Very Large Scale Integration Systems, vol. 9, pp. 90-99, 2001. [15]H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, et al., 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics, in Proceedings International Symposium on Low Power Electronics and Design, 2011, pp. 163-168. [16]D. Nguyen Minh and T. Sakurai, Compact yet high-performance (CyHP) library for short time-to-market with new technologies, in Proceedings of the Asia and South Pacific Design Automation Conference, 2000, pp. 475-480. [17]M. Hashimoto, K. Fujimori, and H. Onodera, Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies, in Proceedings of the Asia and South Pacific Design Automation Conference 2003, pp. 589-590. [18]S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, Scaling of stack effect and its application for leakage reduction, in Proc. International Symposium on Low Power Electronics and Design, 2001, pp. 195-200. [19]Synopsys Liberty NCX User Guide, Dec. 2011. [20]H. Yuan-Hao, M. Hsi-Pin, L. Ming-Luen, and C. Tzi-Dar, A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications, IEEE Journal of Solid-State Circuits, vol. 39, pp. 169-183, 2004. [21]Synopsys DesignWare Building Block IP Documentation Overview, Oct. 2010. [22]L. Shien-Chun, H. Chi-Ray, and C. Lih-Yih, Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion, in Proc. IEEE International Symposium on Circuits and Systems, 2012, pp. 2553-2556. [23]S. Lutkemeier and U. Ruckert, A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror, IEEE Transactions Circuits and Systems II: Express Briefs, vol. 57, pp. 721-724, 2010.
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