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研究生:柯柏州
研究生(外文):Bo-ZhouKe
論文名稱:具有低成本與低能量時間積之次臨界電壓邏輯電路設計
論文名稱(外文):Low Cost and Low Energy-Delay-Product Sub-threshold Logic Design
指導教授:邱瀝毅
指導教授(外文):Lih-Yih Chiou
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:中文
論文頁數:66
中文關鍵詞:次臨界電壓電路設計超低電壓電路設計製程變異容忍力超低功率應用
外文關鍵詞:Sub-threshold logicUltra-low voltage circuitProcess variation tolerantUltra-low voltage application
相關次數:
  • 被引用被引用:0
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  • 下載下載:19
  • 收藏至我的研究室書目清單書目收藏:0
在以能量消耗考量為主的應用中,如可攜式行動裝置、生醫電子系統、以及無線感測器等,將電路操作於次臨界電壓區域為有效降低能量消耗的有效方法之一。然而,將電路操作於次臨界電壓區域會嚴重的降低電晶體驅動電流對漏電流的比值,更增加對製程變異的敏感度,使得電路的強健性下降,導致電路功能容易錯誤,因此為了增加電路操作於次臨界電壓區域的強健性,本論文提出了N傾向型的史密特觸發架構,此架構不僅可以有效的增加邏輯電路驅動電流對漏電流的比值,更可以降低對製程變異的敏感度,使得電路在次臨界電壓區域可以穩定的操作。本論文所提出的架構與史密特觸發邏輯架構[1]在驗證電路乘法累加器中,以台積電90奈米製程做後佈局模擬後的比較,在操作電壓0.2V時,改善6倍的時間能量積並減少40%的面積。

Sub-threshold operation has been shown to be a promising approach for ultra-low power applications, such as portable mobile devices, biomedical electronic systems and wireless sensor network. However, operating logic circuits in the sub-threshold regime would seriously degrade the ratio of transistor driving current to leakage current and increase the sensitivity of process variations, thus increasing the possibility of logic functional failures. To increase the robustness of logic circuit in the sub-threshold regime, we propose a sub-threshold logic style called N-Critical Schmitt-Trigger logic. This structure could not only effectively increase the ratio of logic circuit driving current to leakage current, but also reduce the sensitivity of process variation when operated in the sub-threshold regime. In this thesis, the multiplier and accumulator (MAC) circuits are implemented in TSMC 90nm to demonstrate the feasibility of our proposed N-critical Schmitt-Trigger logic in the sub-threshold regime. According to post-layout simulation results, the MAC circuit implemented with our proposed logic structure shows 40% area overhead reduction and 6x energy-delay-product (EDP) improvement at 0.2V when compared with conventional Schmitt-Trigger logic structure[1].

摘要 i
Abstract ii
致謝 iii
目錄 iv
表目錄 vii
圖目錄 viii
第 1 章 緒論 1
1.1 研究動機 1
1.1.1 功率消耗與能量消耗 1
1.1.2 次臨界電壓操作 3
1.1.3 製程變異 5
1.2 研究重點 7
1.3 研究貢獻 8
1.4 論文架構 9
第 2 章 相關研究 10
2.1 提高驅動電流對漏電流比值方法 10
2.2 改變臨界電壓值的設計方式 11
2.2.1 基底偏壓技術 12
2.2.2 次臨界動態調整臨界電壓電晶體 13
2.2.3 傳輸閘堆疊N型電晶體邏輯架構 15
2.3 改變閘極對源極電壓值的設計方式 16
2.3.1 史密特觸發邏輯架構 16
2.4 總結 17
第 3 章 N傾向型史密特觸發邏輯電路設計 18
3.1 設計問題和分析 18
3.2 N傾向型史密特觸發反向器 20
3.3 N傾向型史密特觸發反或閘 21
3.4 N傾向型史密特觸發反及閘 22
3.4.1 N傾向型史密特觸發反及閘架構分析 23
3.4.2 N傾向型史密特觸發反及閘操作分析 24
3.5 N傾向型史密特觸發正反器 26
第 4 章 次臨界標準元件庫 28
4.1 次臨界標準元件庫 28
4.2 邏輯功能選擇 29
4.3 邏輯閘佈局格式 31
4.4 元件庫產生 33
第 5 章 模擬結果 34
5.1 N傾向型史密特觸發電路之雜訊邊際分析 34
5.2 漏電流抑制效益分析 36
5.2.1 漏電流抑制效益之定量分析 36
5.2.2 漏電流抑制效益之定性分析 38
5.3 N傾向型史密特觸發正反器模擬結果 40
5.4 驗證電路 42
5.5 全晶片架構設計 45
5.6 全晶片佈局圖 48
5.7 全晶片模擬結果 49
5.8 1伏特電壓下模擬比較結果 53
5.8.1 操作速度比較 53
5.8.2 功率消耗比較 54
5.8.3 能量消耗比較 55
5.8.4 能量時間積比較 56
5.9 次臨界電壓模擬比較結果 57
5.9.1 操作速度比較 57
5.9.2 功率消耗比較 58
5.9.3 能量消耗比較 59
5.9.4 時間能量積比較 60
5.10 面積比較 61
第 6 章 結論和未來工作 62
6.1 結論 62
6.2 未來工作 63
參考文獻 64
個人簡歷 66

[1]N. Lotze and Y. Manoli, A 62 mV 0.13 um CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic, IEEE Journal of Solid-State Circuits, vol. 47, pp. 47-60, 2012.
[2]A. Wang and A. Chandrakasan, A 180-mV subthreshold FFT processor using a minimum energy design methodology, IEEE Journal of Solid-State Circuits, vol. 40, pp. 310-319, 2005.
[3]J. Wei, L. Sheng, H. Weifeng, and M. Zhigang, A 230mV 8-bit sub-threshold microprocessor for wireless sensor network, in IEEE International Conference on VLSI and System-on-Chip, 2011, pp. 126-129.
[4]B. H. Calhoun, A. Wang, N. Verma, and A. Chandrakasan, Sub-Threshold Design: The Challenges of Minimizing Circuit Energy, in Proceedings International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
[5]N. Verma, J. Kwong, and A. P. Chandrakasan, Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits, IEEE Transactions on Electron Devices, vol. 55, pp. 163-174, 2008.
[6]F. F. a. M. PEDRAM, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, IEICT TRANS. ELECTRON, vol. E88-C, 2005.
[7]C. Jinhui, L. T. Clark, and C. Yu, Maximum - Ultra-low voltage circuit design in the presence of variations, Circuits and Devices Magazine, IEEE, vol. 21, pp. 12-20, 2006.
[8]K. A. Bowman, S. G. Duvall, and J. D. Meindl, Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration, IEEE Journal of Solid-State Circuits, vol. 37, pp. 183-190, 2002.
[9]A. R. Brown, G. Roy, and A. Asenov, Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture, IEEE Transactions on Electron Devices, vol. 54, pp. 3056-3063, 2007.
[10]J. Kwong, Y. K. Ramadass, N. Verma, and A. P. Chandrakasan, A 65 nm Sub-Vt Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter, IEEE Journal of Solid-State Circuits, vol. 44, pp. 115-126, 2009.
[11]M. Alioto, Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial, IEEE on Transactions Circuits and Systems I: Regular Papers, vol. 59, pp. 3-29, 2012.
[12]N. Reynders and W. Dehaene, A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques, in Proc. IEEE Asian Solid State Circuits Conference, 2011, pp. 113-116.
[13]H. Myeong-Eun, A. Raychowdhury, K. Keejong, and K. Roy, A 85mV 40nW Process-Tolerant Subthreshold 8x8 FIR Filter in 130nm Technology, in Proc. IEEE Symposium on VLSI Circuits, 2007, pp. 154-155.
[14]H. Soeleman, K. Roy, and B. C. Paul, Robust subthreshold logic for ultra-low power operation, IEEE Transactions on Very Large Scale Integration Systems, vol. 9, pp. 90-99, 2001.
[15]H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, et al., 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics, in Proceedings International Symposium on Low Power Electronics and Design, 2011, pp. 163-168.
[16]D. Nguyen Minh and T. Sakurai, Compact yet high-performance (CyHP) library for short time-to-market with new technologies, in Proceedings of the Asia and South Pacific Design Automation Conference, 2000, pp. 475-480.
[17]M. Hashimoto, K. Fujimori, and H. Onodera, Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies, in Proceedings of the Asia and South Pacific Design Automation Conference 2003, pp. 589-590.
[18]S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, Scaling of stack effect and its application for leakage reduction, in Proc. International Symposium on Low Power Electronics and Design, 2001, pp. 195-200.
[19]Synopsys Liberty NCX User Guide, Dec. 2011.
[20]H. Yuan-Hao, M. Hsi-Pin, L. Ming-Luen, and C. Tzi-Dar, A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications, IEEE Journal of Solid-State Circuits, vol. 39, pp. 169-183, 2004.
[21]Synopsys DesignWare Building Block IP Documentation Overview, Oct. 2010.
[22]L. Shien-Chun, H. Chi-Ray, and C. Lih-Yih, Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion, in Proc. IEEE International Symposium on Circuits and Systems, 2012, pp. 2553-2556.
[23]S. Lutkemeier and U. Ruckert, A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror, IEEE Transactions Circuits and Systems II: Express Briefs, vol. 57, pp. 721-724, 2010.

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