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研究生:林虹鳴
研究生(外文):Hung-Ming Lin
論文名稱:應用於K-Band &V-Band之功率放大器
論文名稱(外文):A COMS Power Amplifier for K-Band & V-Band applications
指導教授:林佑昇林佑昇引用關係
指導教授(外文):Yo-Sheng Lin
口試委員:梁效彬杜順利
口試日期:2013-07-29
學位類別:碩士
校院名稱:國立暨南國際大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2013
畢業學年度:101
語文別:英文
論文頁數:82
中文關鍵詞:功率放大器PAEK頻段V頻段疊接共源級Wilkinson功率分配器發射機
外文關鍵詞:Power amplifier (PA)Power added efficiency (PAE)K-bandV-bandcascodeWilkinson power divider/combinertransmitter
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本論文以高增益與高功率之功率放大器為主要的研究目標。我們設計與實現了兩顆不同頻帶的功率放大器。研究主軸可分成兩部分:
第一個部分:我們利用了0.18μm CMOS的製程設計並且實現一顆應用於K-Band的高增益之功率放大器。在電路架構方面,我以基本的三級疊接架構來實現,疊接的目的可用來消除米勒效應對電路帶來的影響,也可以改善反向隔離度。以達到高增益之目的。量測結果顯示此電路操作在22~26GHz時,增益(S21) 為23dB,飽和輸出功率(Psat)為13.75dBm,最大功率附加效率(PAE)為13.98%,而電路整體消耗之功率為131.5mW,且不含 test pads 0.83571 mm2 x 0.7229 mm2。依照量測結果可以得知此電路有著不錯的特性並且適合應用於K頻帶的發射機系統。
第二部分:是一個使用了TN90RF的製程實現於應用在V-Band的功率放大器,電路架構分為三級,第一級為基本的疊接架構,第二級為基本的共源級(CS)架構來實現,主要是因為疊接架構能得到較好的增益以及改善反隔離度,線性度與功率消耗都差於共源級的架構,因此,為了取得數據上的平衡,才會第一級使用疊接的架構第二級使用共源級的架構。而最後一級我們則是使用了功率等分(Power splitting/combining)的架構來實現,主要的目的是為了能夠達成高輸出增益與高功率的功率放大器,模擬結果增益(S21) 為11.742± 1.49dB,飽和輸出功率(Psat)為11.37dBm,最大功率附加效率(PAE)為15.81%,而電路整體消耗之功率為44.4mW,且不含 test pads 0.7332 mm2 x 0.57535 mm2。
本電路在整體消耗功率上有突出的表現。此電路非常適合整合於V頻帶的發射機系統中。

The purpose of thesis is to research high gain and high efficiency power amplifier. We design and realize two power amplifiers, which apply for different frequency. The thesis can be divided into two parts:
The first part is on design and realize of the high gain power amplifier for K-band applications in 0.18μm CMOS technology. In this circuit, We used the cascade-stage structure three stage to eliminate to Miller effect and improve reverse isolation. In order to achieve high gain. The measured results show that this circuit operating 21GHz~24GHz, the gain (S21) is 23 dB, saturation output power is 13.75dBm, max power added efficiency (Peak PAE) is 13.98dBm, total power consumption is 131.98 mw and the chip area(excluding test pads) is 0.83571 mm2 x 0.72285 mm2, these results indicate that this circuit performs well for K-band transmitter systems.
The second part is on the design V-band power amplifier in TN90RF process, The circuit could divided into three stages. The first stage is using cascade-stage, which have better power gain and improve the isolation. But linearity and power consumption are worse than common source stage. Therefore, the second stage is using common source topology. The circuit final stage is using power splitting/combining. In order to achieve the high power gain and high power added efficiency. The circuit simulation results for operating 57GHz~64GHz. Gain(S21) = 12.52±1.3dB saturation output power (Psat) is 9.762dBm, max power added efficiency is 8.5dBm, total power consumption is 62.4mW and chip area is 0.7332 mm2 x 0.57535 mm2,This power amplifier is performs well for V-Band transmitter systems.

Contents

Contents…………………………………...……………………i
List of Figures…………………………...……………………..v
List of Tables……………………………….…………………ix

Chapter 1 Introduction...............1
1.1 Motivation……………………………………………………………1
1.2 What is Power Amplifier?.………..………………………............4
1.3 Thesis Organization…………………………………………..............6

Chapter 2 Basic Theories of Power Amplifier....7
2.1 Power Amplifier Classification…………………………………….7
2.1.1 Class A, B, AB and C Power Amplifiers………………………9
2.1.1.1 Class A……………………………………………….9
2.1.1.2 Class B………………………………………………11
2.1.1.3 Class AB……………………………………………13
2.1.1.4 Class C………………………………………………14
2.1.2 Class D, E, F Power Amplifiers……………………15
2.1.2.1 Class D……………………………………………………15
2.1.2.2 Class E………….…………………………………………16
2.1.2.3 Class F……………………………..……………………...17
2.2 Power amplifier basic circuit………………………………………18
2.2.1 Common source……………….……………………………18
2.2.2 Cascode……………………………………………………20
2.3 Power Amplifier Parameter Definitions……………………….................21
2.3.1 Scattering Parameters………………..………….…………….…21
2.3.2 Stability…………………………..……….………………….….22
2.3.3 Power Gain…………………………………………………24
2.3.3.1 Transducer power gain (GT): ………………………...…….24
2.3.4 Output power and 1dB gain compression point (P1dB)……….....…25
2.3.5 Saturated power (Psat)…………...…………………………………26
2.3.6 3rd-order intercept point (IP3)……………..……………...………26
2.3.7 Power Efficiency……………………………………….………….29
2.3.7.1 Total efficiency (ηT) :……………………………….29
2.4 Design Procedure and Consideration………………………….…………30
Chapter 3 The High gain Power Amplifier for K-band
applications in 0.18μm CMOS Technology............32
3.1 Introduction………………………………………………………32
3.2 Circuit Design……………………………………………………33
3.3 Results and Discussion…………………………………………34
3.3.1 Simulation and Measurement Results of Power Amplifier…34
3.4 Conclusion………………………………………………………47
Chapter4 A CMOS Power Amplifier for V band applications.......48
4.1 Introduction…………………………………………………………48
4.2 Circuit Design………………………………………………………52
4.3 Results and Discussion…………………………………..…………55
4.3.1Simulation Results of Power Divider/Combiner..55
4.3.2 Power Divider/Combiner of simulation result…………………56
4.3.3 Simulation and Measurement Results of Power Amplifier…..59
4.4 Conclusion……….…………………………………………………73
Chapter 5 Conclusion and Future Work.......74
5.1 Conclusion…………………………………………………………74
References…………………………………………………...75
Appendix…………………………………………………….78
Vita…………………………………………………………..82

List of Figures

Fig 1.1 Wireless communication system…………...……………………………………… 1
Fig 1.2 Philips’s GSM system………………………………………...………………….. 4
Fig 2.1 Classification of power amplifier………………………………...………………… 8
Fig 2.2 Class A Power amplifier………………………………………...………………….10
Fig 2.3 The input voltage and drain current waveforms of Class A power amplifier……………………………………………………………………………………10
Fig 2.4 Class B power amplifier………………………………………………………….. 12
Fig 2.5 Class AB Power amplifier………………………………………………………… 13
Fig 2.6 Class C Power amplifier………………………...………………………………... 14
Fig 2.7 Class D power amplifier………………………….………………………………. 16
Fig 2.8 Class E power amplifier……………………………...…………………………… 17
Fig 2.9 Class F Power amplifier……………………………………………………………18
Fig 2.10 Common source………………………………………….……………………… 19
Fig 2.11 Small signal model……………..………………………...……………………… 19
Fig 2.12 Cascode basic circuit…………………………………………….………………. 20
Fig 2.13 Two port network [5]……...….……………………………………….………… 22
Fig 2.14 The available and actual power in the two-port network………………..………. 24
Fig 2.15 Pout、P1dB and Psat ………..…….……………………………………...…………. 25
Fig 2.16 The input and output spectrum of a nonlinear system………………..…………. 28
Fig 2.17 The 3rd-order intercept point (IP3)…………………………………...…………. 28
Fig 2.18 The diagram of power efficiency………………………………….…………….. 29
Fig 2.19 Power amplifier design flow chart……………………………...……………….. 31
Fig 3.1 References [7] of the power amplifier schematic………………………………… 33
Fig 3.2 Power amplifier circuit………………………………………...…………………. 33
Fig 3.3(a) S11 simulation of result……………………………..……………………………36
Fig 3.3(b) S11 measurement of result……………………..…………………………….......36
Fig 3.4(a) S22 simulation of result…………………….……………………………………37
Fig 3.4(b) S22 measurement of result…………………………..…………………………...37
Fig 3.5(a) S21 simulation of result…………………………….…………………………....38
Fig 3.5(b) S21 measurement of result…………………………..…………………………...38
Fig 3.6(a) S12 simulation result……………………………………..……………………....39
Fig 3.6(b) S12 measurement result……………………………………..…………………...39
Fig 3.7(a) IIP3&OIP3 simulation of result…………….……………….……………..…....40
Fig 3.7(b) IIP3&OIP3 measurement of result………………….…………………………..40
Fig 3.7(c) PAE simulation of result………………………….……………………………..41
Fig 3.7(d) PAE measurement of result……………………….…………………………….41
Fig 3.7(e) OP1dB&IP1dB simulation of result………………...…………………………..42
Fig 3.7(f) OP1dB&IP1dB measurement of result………………………………………….42
Fig 3.7(g) Psat simulation of result………………………………...……………………… 43
Fig 3.7(h) Psat measurement of result……………………………..………………………..43
Fig 3.8(a) Simulation u result……………..……………………………………………...44
Fig 3.8(b) Measurement u result…………………………………..……………………….44
Fig 3.9 The chip die photo…………………………...……………………………………..47
Fig 4.1 60GHz power amplifier schematic…………….……..………………………........49
Fig 4.2 Wilkinson divider/combiner is basic architecture[14]…………….……………….50
Fig 4.3 (a) Schematic diagram of 8-Way Power amplifier [15]…………………..………..51
Fig 4.3 (b) Schematic diagram of 2-Way Power amplifier [15]………………………...… 52
Fig 4.4 (a) Circuit diagram…………………………………….……………………….. …52
Fig 4.4 (b) Chip micrograph of the proposed PA…………………………………………..53
Fig 4.5 Lossless mode…………………………………………………………...…………54
Fig 4.6 Wilkinson power divider……………………………………………...…………....55
Fig 4.7 S-parameter matrix of an ideal Wilkinson power divider ………………………56
Fig 4.8 Simulation of transmission gains S21 & S31versus frequency characteristic……….57
Fig 4.9 Simulation of retune loss S11 & S22&S33 versus frequency characteristic………57
Fig 4.10 Simulation of transmission gains S21 & S31 versus frequency characteristics of Wilkinson power combiner……………………………………………………………….58
Fig 4.11 Simulation of retune loss S11 & S22 & S33 versus frequency characteristics of Wilkinson power combiner……………………..………………………………………….58
Fig 4.12(a) S11 simulation of result……………..………………………………………… 61
Fig 4.12(b) S11 measurement of result………………..…………………………………… 61
Fig 4.13(a) S22 simulation of result…………………………………………………..…….62
Fig 4.13(b) S22 measurement of result……………………………………………………. 62
Fig 4.14(a) S21 simulation of result………………………………………………..……….63
Fig 4.14(b) S21 measurement of result…………………………………………..…………63
Fig 4.15(a) S12 simulation of result………………………………………………………...64
Fig 4.14(b) S21 measurement of result…………………………………...………………...64
Fig4.15(a) Stability simulation of result…………………………….……………………. 65
Fig4.15(b) Stability measurement of result………………………….……………………..65
Fig 4.16(b) IIP3&OIP3 measurement of result…………………………………………….66
Fig 4.16(a) IIP3&OIP3 simulation of result………………………..……………………... 66
Fig 4.16(c) PAE simulation of result……………………………….………………………67
Fig 4.16(d) PAE measurement of result…………………………...……………………… 67
Fig 4.16(e) IP1dB&OP1dB simulation of result…………………………………………...68
Fig 4.16(f) IP1dB&OP1dB measurement of result…………………………………….......68
Fig 4.16(g) Psat simulation of result…………………………..……………………………69
Fig 4.16(h) Psat measurement of result…………………………...……………………….. 69
Fig. 4.17 Simulated and Gms/GAmax versus frequency characteristics of the input transistor M1……………………………………………………..…....................................70

List of Tables

Table 1.1 RF technology progress………………………………..………………….………2
Table 1.2 The comparison between different device technologies…………………….…….3
Table 2.1 The properties of power amplifier in different bias class………………………....8
Table 3.1 Summary of the simulation and measurement results ……….........…………….45
Table 3.2 Summary of the implemented CMOS Pas …………………………….………...46
Table 4.1 The summary of simulation and measurement result…………..………………..71
Table 4.2 shows the comparison with the results of pro-simulation, measurement of power amplifier and the CMOS V-band PAs in references………………………………………72












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