臺灣博碩士論文加值系統

在此篇論文中，我們提出了兩種多執行緒的Java執行環境，包括單一核心以硬體切換不同執行緒的 Temporal Multithreading (TMT)，以及多核心並行的 Simultaneous Multithreading(SMT)。首先在單一Java核心TMT架構方面，因為Java本身就是一種多執行緒的程式語言，而每個執行緒都擁有自己的執行資訊與運算堆疊。若是利用多組硬體堆疊來維護所有執行緒的狀態，對於嵌入式系統設計的成本過大。因此，在我們的設計中提出了兼具效能與成本的解決方案，將各執行緒所運作的堆疊資料在DDR-SDRAM中存有備份，並在Java處理器中利用兩組運算堆疊，當處理器在執行時使用其一的堆疊運算，並將另一堆疊準備好提供接續的執行緒可順利執行。對於執行緒的管理完全是由Java處理器核心負責。實驗顯示，所提供的架構在多執行緒環境下支援執行緒的切換是較有效率的。而第二種SMT則是多處理核心的執行環境，利用在系統中加入多組Java處理核心，使得執行緒的運作可以並行執行。並且由於在執行時的各處理器上的Heap資料可能會不一致，因此我們設計了一個處理資料一致性的機制來確保執行的正確性。結果顯示，在多核心的架構下使得執行緒平行執行確實可以提高執行效率。而我們所提出的Java處理器架構也在Xilinx ML-605 FPGA平台上實作驗證。

摘要 I
誌謝 II
目錄 III
圖目錄 V
表目錄 VII
第一章 前言 1
1.1. 研究動機 1
1.2. Java執行環境 2
1.3. 論文架構 4
第二章 相關研究 5
2.1. 異質雙核心Java處理器 5
2.2. 多執行緒相關研究 9
第三章 Temporal Multithreading系統架構 13
3.1. Thread Manager Unit 14
3.1.1. 執行緒新增與終結 16
3.1.2. Thread Controller 17
3.1.3. Thread Control Block 21
3.1.4. 執行緒佇列 23
3.1.5. Stack Manager 25
3.1.6. 執行緒同步 27
3.2. Ping-pong Java stack memory 28
3.3. 系統軟體 30
3.3.1. 呼叫方法流程 31
3.3.2. Method Flag 34
3.3.3. 類別解析器對於新增執行緒之設計 35
3.3.4. 硬體原生方法介面 37
第四章 多處理核心系統架構 39
4.1. 多處理器執行環境 40
4.2. Object Heap Cache 44
4.3. Data Coherence Controller 47
4.3.1. Heap Cache Coherence之機制 48
4.3.2. Java同步機制之支援 50
第五章 實驗結果 52
5.1. 實驗環境 52
5.2. Benchmark分析 53
5.2.1. Single-Thread效能分析 53
5.2.2. Temporal Multithreading效能分析 54
5.2.3. 多處理核心效能分析 55
第六章 結論與未來展望 57
參考文獻 58

[1]B. R. Montague, “JN: OS for an Embedded Java Network Computer,” IEEE Micro, 17, 3, pp. 54-60,1997.
[2]J.M. O'Connor and M. Tremblay, “picoJava-I: the Java virtual machine in hardware,” Micro, IEEE, vol. 17, no. 2, pp. 45-53, Mar./Apr. 1997.
[3]3. Sun Microsystems, J2ME Technology, Sun Developer Network URL: http://java.sun.com/javame/technology/, 1994-2009.
[4]C.-M. Chung and S.-D, Kim, “A dualthreaded Java processor for Java multithreading,” In Proc. IEEE on Parallel and Dist. Sys, pp. 693-700, 1998.
[5]J. Kreuzinger, et al, “Real-time event-handling and scheduling on a multithreaded Java microcontroller. Microprocessors and Microsystems,” , 27.1: pp.19-31, 2003.
[6]C. Pitter and M. Schoeberl, “Towards a Java multiprocessor,” In Proc. of the 5th ACM int. workshop on Java technologies for real-time and embedded systems, pp. 144-151,2007.
[7]A. Wellings and M. Schoeberl, “Thread-local scope caching for real-time Java, IEEE ISORC'09, pp. 275-282, 2009.
[8]M. W. El-Kharashi and F. Elguibaly, “Java Microprocessors: Computer Architecture Implications,” Proc. of IEEE Pacific Rim Conf. on Comm., Computers, and Signal Proc., vol. 1, pp. 277-280, Aug. 1997..
[9]K. B. Kent and M. Serra, “Hard/Software Co-Design of a Java Virtual Machine,” Proc. of IEEE Int. Workshop on Rapid Systems Prototyping (RSP), June, 2000.Sun Microsystems, Connected, Limited Device Configuration Specification, ver. 1.0a, Sun Microsystems White Paper, May 2000.

[10]White, James. "An introduction to Java 2 micro edition (J2ME); Java in small things. “ Proceedings of the 23rd international conference on Software engineering,” IEEE Computer Society, 2001.
[11]Bill Venners, Inside the Java 2 Virtual Machine, New York: McGraw-Hill, 2001, ch.5 ch.6 ch.7 ch.8.A. Krall, “Efficient Java Just-in-Time Compilation,” Proc. of Int. Conf. on Parallel Architectures and Compilation Techniques, pp. 205-212, Paris, Oct. 1998.
[12]The Java Community Process Program, JSR 36: Connected Device Configuration, ver. 1.0b,Dec 20, 2005.
[13]Connected, Limited Device Configuration Specification Version 1.0a, Sun Microsystems
White Paper, May. 2000.
[14]Jun Qin, Qiaomin Lin, and Xiujin Wang, Research on Embedded Java Virtual Machine and its Porting, IJCSNC International Journal of Computer Science and Network Security, Vol.7 No.9, September 2007.
[15]ARM inc, “Jazelle technology: ARM acceleration technology for the Java Platform”, 2004.
[16]Nazomi Communication, inc, “JSTAR-Java Coprocessor for ARM Microprocessors”.
[17]Sun Inc, ”picoJava-II Processor Core”, Datasheet,1999.
[18]Harlan McGhan, Mike O’Connor, “PicoJava: A Direct Execution Engine For Java Bytecode”,IEEE 1998.
[19]Ajile Inc, “aJile Java Processor Core JEMCore”, 2001.
[20]Ajile Inc, “aJ-100 TM Real-time Low Power Java TM Processor”,Processor Datasheet, 2001.
[21]A. Krall, “Efficient Java Just-in-Time Compilation,” Proc. of Int. Conf. on Parallel Architectures and Compilation Techniques, pp. 205-212, Paris, Oct. 1998.Sun, picoJava-II Microarchitecture Guide, Sun Microsystems, March 1999.
[22]C.-H. Hsieh, J. C. Gyllenhaal, and W. W. Hwu, “Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results,” Proc. of 29th Annual ACM/IEEE Int. Symp. on Microarchitecture (MICRO’29), pp. 90-99, Paris, Dec. 1996.H. McGhan and M. O’Connor, “PicoJava: A Direct Execution Engine for Java Bytecode,” Computer, Vol. 31, Issue 10, pp. 22-30, Oct. 1998.
[23]U. Brinkschulte, C. Krakowski, J. Kreuzinger, and T. Ungerer, “A Multithreaded Java Microcontroller for Thread-Oriented Real-Time Event-Handling,” Proc. of 1999 Int. Conf. on Parallel Architectures and Compilation Techniques (PACT’99), pp. 34-39, Newport Beach, Oct. 1999
[24]M. Schoebel, “Evalution of a Java Processor,” Tagungsband Austrochip 2005, pp. 127-134, Oct. 2005.
[25]H.-J. Ko and C.-J. Tsai, “A Double-issue Java Processor Design for Embedded Application,” Proc. of IEEE Int. Symp. on Circuits and Systems(ISCAS’08), Seattle, May. 2007.
[26]H.-J. Ko, “A Double-issue Java Processor Design for Embedded Application, ” Mater thesis, NCTU, 2007.
[27]Cheng-Che Chen, Ying-Tien Huang, Chen-Hung Yang, “Java Virtual Machine on CCL Java Coprocessor, ” CCL Technical Journal, no. 103, , pp56-67, Mar 2003.
[28]H.-W. Kuo, “Design of Java Accelerator IP for Embedded Systems, ” Mater thesis, NCTU, 2011.
[29]Z.-J. Guo, “Design of Dual-Core Java Application Processor for Embedded Systems, ” Mater thesis, NCTU, 2012
[30] Z.-G. Lin, H.-W. Kuo, Z.-J. Guo, and C.-J. Tsai, “Stack Memory Design for a Low-Cost Instruction Folding Java Processor,” IEEE ISCAS, May, 2012.
[31]Z.-G. Lin, “Design of stack memory device and system software for java accelerator IP, ”Mater thesis, NCTU, 2011.
[32]S. Ritchie, “Systems Programming in Java,” IEEE Micro, 17, 3 (Mar.), 1997, pp. 30-35.
[33]Ungerer, Theo, Borut Robič, and Jurij Šilc. “Multithreaded processors,” The Computer Journal 45.3 pp.320-348, 2002.
[34]Tullsen, Dean M., et al. “Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor,”ACM SIGARCH Computer Architecture News. Vol. 24. No. 2. ACM, 1996.
[35]Martin Schoberl, “JOP: A Java Optimized Processor for Embedded Real-Time Systems,” Ph.D.Thesis, Tech. Universitaet Wien, Jan 2005.