跳到主要內容

臺灣博碩士論文加值系統

(18.97.14.82) 您好!臺灣時間:2025/02/19 10:46
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:蔡明甫
研究生(外文):Tsai, Ming-Fu
論文名稱:奈米尺度多重閘極金氧半場效電晶體之靜態隨機存取記憶體的設計與分析特性
論文名稱(外文):Design and Characterization of SRAM in Nanoscale Multi-Gate MOSFETs
指導教授:莊景德
指導教授(外文):Chuang, Ching-Te
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:101
語文別:英文
論文頁數:69
中文關鍵詞:電流拴鎖型感應放大器鰭狀場效電晶體獨立閘極控制奈米線狀場效電晶體線邊緣粗糙程度
外文關鍵詞:Current-Latch-based Sense AmplifierFinFETindependently-controlled-gateNanowire MOSFETLine Edge Roughness
相關次數:
  • 被引用被引用:0
  • 點閱點閱:290
  • 評分評分:
  • 下載下載:21
  • 收藏至我的研究室書目清單書目收藏:0
本論文包含了兩個主題並如同下面的方式排列。第一,我們提出了三種應用於奈米尺度Bulk-CMOS技術下的電流拴鎖型感應放大器 (Current-Latch-based Sense Amplifier) 以及多種運用獨立閘極控制 (independently-controlled-gate) 鰭狀場效電晶體 (FinFET) 的電流拴鎖型感應放大器。第二,我們在TCAD平台上提出了一個用來模擬奈米線狀場效電晶體 (Nanowire MOSFET)二維線邊緣粗糙程度 (Line Edge Roughness) 的方法。上述的兩個研究成果將在第二及第三段做簡單的描述。

在第一個研究中,由廣泛的模擬結果可得知我們提出的架構非常堅固,可抵抗隨機補償錯誤。我們提出的電流拴鎖型感應放大器可以大幅壓抑補償電壓的能力,在40nm Bulk-CMOS (25nm FinFET-SOI) 的技術下與傳統電流拴鎖型感應放大器比較,補償電壓的變異最高可以有74% (76%)的降低。同時,可以最多減少27% (52%) 的感應時間,以及可以最多少71% (77%) 的Time-To-Sense時間,bit-line的功率消耗可以降低73% (76%)。最後我們提出的電流拴鎖型感應放大器可以大幅的提升感應良率,一條bit-line可承受的cell個數,因此強化了array的使用效率、全部面積、表現能力和功率。

在第二個線狀場效電晶體的研究中,我們提出來的方法相較於先前文獻所使用的兩種一維型態變異[1]可以更精確的預測元件特性和變異。根據所提出來的模擬方法,我們運用了三維TCAD模擬器和蒙地卡羅 (Monte Carlo) mixed-mode 模擬在Wire-LER變異性對元件特性、操作在次臨界區6T SRAM及邏輯電路穩定性的衝擊上做了完整的分析。以上的結果皆會與先前文獻的方法做比較來顯示出用一維型態變異的模型和預測的不足。

This thesis contains two topics and is organized as follows. First, we propose three Current-Latch-based Sense Amplifiers (CLSA) configurations for nanoscale Bulk-CMOS SRAM and several CLSAs using FinFET devices with independently-controlled-gate. Second, a methodology to simulate realistic 2D Line Edge Roughness (LER) pattern for NanoWire (NW) MOSFETs is proposed in TCAD platform. The simple description of above two topics is arranged in the second and third paragraph separately.

In the first work, extensive simulations suggest the proposed CLSAs are robust against random offset errors. The proposed structures feature significant offset suppression capabilities with σoffset reduction up to 74% (76%) in 40nm Bulk-CMOS (25nm FinFET-SOI) technology compared with the conventional CLSA. Meanwhile, up to 27% (52%) shorter sensing delay, 71% (77%) shorter Time-To-Sense and 73% (76%) lower bit-line power consumption are achieved in 40nm Bulk-CMOS (25nm FinFET-SOI). Finally, the proposed CLSA structures significantly enhance the sensing yield and affordable number of cells per bit-line, thus improving the array efficiency hence overall area and performance/power as well.

In the second study in NW MOSFETs, the proposed approach predicts the device characteristic and variations more accurately compared with prior literature considering two types of primarily 1D NW geometry variation [1]. Based on the proposed simulation approach, we carry out a comprehensive analysis using 3D atomistic TCAD and mixed-mode Monte Carlo simulations on the impacts of Wire-LER on the variability of device characteristics, stability of 6T SRAM operating in subthreshold region and logic circuits. The results are extensively compared with previous approaches to illustrate the deficiency of modeling and predictions based on 1D NW geometry variation.

Abstract (Chinese) I
Abstract (English) II
Acknowledgement III
Contents IV
Figure Captions V
Table Captions VIII

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation and Goals 2
1.3 Thesis Organization 3
Chapter 2 Variation Tolerant CLSAs for Nanoscale Bulk-CMOS and FinFET SRAM 4
2.1 Introduction 4
2.2 CLSA Structures and Operations 6
2.3 CLSA Sensing Delay 7
2.4 Input Offset Voltage and Yield 8
2.5 Time-To-Sense and BL Power Consumption 12
2.6 CLSAs Using FinFET Devices 12
2.6.1 Introduction 12
2.6.2 Analysis of Loacal Random Variation – Line Edge Roughness (LER) and Work Function Variation (WFV) 13
2.6.3 Results and Discussions 15
2.7 Summary 16
Chapter 3 Impacts of Wire-LER on Nanowire MOSFET Devices, Subthreshold SRAM and Logic Circuits 45
3.1 Introduction 45
3.2 Methodology to Construct Wire-LER 46
3.3 Impacts of Wire-LER on NW MOSFET Characteristics 47
3.4 Stability of Subthreshold 6T SRAM Cells 48
3.5 Logic Circuit Performance 49
3.6 Summary 49
Chapter 4 Conclusions 63
References
[1] R. Wang, et. al., “Investigation on Variability in Metal-Gate Si Nanowire MOSFETs: Analysis of Variation Sources and Experimental Characterization,” IEEE TED, vol.58, no.8, pp.2317-2325, Aug. 2011.
[2] T. Kobayashi, et. al., “A current controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,” IEEE JSSC, vol. 28, pp. 523–527, Apr., 1993.
[3] K. Seno, et. al., “9 ns 16 Mb CMOS SRAM with offset reduced current sense amplifier,” ISSCC, pp. 248 - 249, 297, Feb. 1993.
[4] A. T. Do, et. al., “0.9 V current-mode sense amplifier using concurrent bit- and data-line tracking and sensing techniques,” Electron. Lett., vol. 43, pp. 1421–1422, 2007.
[5] R. Sarpeshkar, et. al., “Mismatch sensitivity of a simultaneously latched CMOS sense amplifier,” IEEE JSSC, vol.26, pp.1413-1422, Oct., 1991.
[6] B. Wicht, Current Sense Amplifier for Embedded SRAM in High-Performance System-on-a-Chip Designs. New York: Springer-Verlag, 2003.
[7] B. Wicht, et. al., “Yield and speed optimization of a latch type voltage sense amplifier”, IEEE JSSC, vol. 39, pp. 1148-1158, July, 2004.
[8] A. Asenov, “Simulation of statistical variability in nano MOSFETs,” in IEEE Symp. VLSI Technol., Dig. Tech. Papers, pp. 86–87, Jun. 2007.
[9] T. Matsukawa, et. al., “Comprehensive analysis of variability sources of FinFET characteristics,” in VLSI Symp.Tech, pp.118-119, June, 2009.
[10] E. Baravelli, et. al., “Impact of Line-Edge Roughness on FinFET Matching Performance,” IEEE TED, vol.54, pp.2466-2474, Sept., 2007.
[11] A.R.Brown, et. al., “Intrinsic parameter fluctuations in MOSFETs due to structural non-uniformity of high-κ gate stack materials,” SISPAD, pp. 27- 30, 2005.
[12] Ming-Long Fan, et. al., “Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability—A Model-Based Approach,” IEEE TED, vol.58, pp.609-616, March, 2011.
[13] S. Mukhopadhyay, et. al., “A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET,” IEEE TVLSI, vol. 14, pp. 183–192, Feb., 2006.
[14] A. Choudhary, S. Kundu, “A Process Variation Tolerant Self-Compensating Sense Amplifier Design,” IEEE ISVLSI, pp. 263–267, May, 2009.
[15] S. Mukhopadhyay, et. al, “Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM,” in Proceedings of Test Symposium, pp. 176–181, Dec. 2006.
[16] “Sentaurus TCAD, C2009-06 Manual,” Sentaurus Device, 2009.
[17] Anh-Tuan Do, et. al., “Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier," IEEE Transactions on , vol.57, pp.83-92, Jan., 2010.
[18] Hyunwoo Nho, et. al., “Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation," IEEE Trans. on Circuits Syst. II: Exp. Briefs , vol.55, pp.907-911, Sept., 2008.
[19] http://www.intel.com
[20] D. Hisamoto, et. al., “FinFET—A self-aligned double-gate MOSFET scalable to 20 nm,” IEEE TED, vol. 47, pp. 2320–2325, Dec., 2000.
[21] Y. Liu, et. al., “A highly Vth-controllable 4T FinFET with an 8.5-nmthick Si-fin channel,” IEEE EDL, vol. 25, pp. 510–512, Jul., 2004.
[22] S. M. Goodnick, et. al., “Surface Roughness at the Si(100)-SiO2 interface, “ Physical Review B, vol. 32, pp. 8171-8186, 1985.
[23] A. Asenov, et. al., “Intrinsic Parameter Fluctuations in Decananometer MOSFETs Introduced by Gate Line Edge Roughness,” IEEE Transactions on Electron Devices, vol. 50, no. 5, pp. 1254-1260, May 2003.
[24] K. Ohmori, et. al., “Impact of Additional Factors in Threshold Voltage Variability of Metal/High-k Gate Stacks and Its Reduction by Controlling Crystalline Structure and Grain Size in the Metal Gates” IEDM, pp. 1-4, Dec. 2008.
[25] X. Zhang, et. al., “Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability” IEDM, pp. 1-4, Dec. 2009.
[26] S. H. Chao, et. al., “Investigation and Comparison of Work Function Variation for FinFET and Ultra-Thin-Body SOI Devices Using a Voronoi Approach” SSDM, 2012.
[27] T.S. Doorn, et. al., “Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield," ESSCIRC, pp.230-233, Sept., 2008.
[28] Adel S. Sedra, Kenneth C. Smith, “Microelectronic Circuits” 5rd ed. Oxford University Press, 2003.
[29] Y. Tian, et. al., “New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CMOS Technology: Process Integration, Experimental Characterization of Carrier Transport and Low Frequency noise,” IEDM, pp.895-898, 2007.
[30] S. D. Suk, et. al., “High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability,” IEDM, pp.717-720, 2005.
[31] N. Singh, et. al., “Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance,” IEDM, pp.1-4, 2006.
[32] R. Wang, et. al., “New observations of suppressed randomization in LER/LWR of Si nanowire transistors: Experiments and mechanism analysis,” IEDM, pp.34.6.1-34.6.4, 2010.
[33] S. Bangsaruntip, et. al., “Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm,” Symposium on VLSI Technology, pp.21-22, 2010.
[34] A. Asenov, et. al., “Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Transactions on Electron Devices, vol.50, no.9, pp. 1837- 1852, Sept. 2003.
[35] E. Baravelli, et. al., “ ESSDERC, pp.415-418, 2009.
[36] R. Sarpeshkar, et. al., “Mismatch sensitivity of a simultaneously latched CMOS sense amplifier,” IEEE JSSC, vol. 26, pp. 1413 - 1422, Oct. 1991.
[37] S. Rodrigues and M. S. Bhat, “Impact of process variation induced transistor mismatch on sense amplifier performance,” in Proc. Int. Conf. on Adv. Computing Commun., pp. 497–502, 2006.



連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top