臺灣博碩士論文加值系統

本篇論文探討和綜合比較鰭狀(FinFET)及三閘極(Trigate)場效電晶體在數位邏輯電路(Logic circuits)、靜態隨機存取記憶體(SRAM)穩定度和維德拉電流源(Widlar Current Source)之研究和分析。在關鍵本質參數變異部分，我們使用3D數值模擬軟體考慮了鰭線邊緣粗糙度（fin Line Edge Roughness），功函數變異程度（Work Function Variation）與單一電荷造成的隨機電報雜訊（Random Telegraph Noise）在鰭狀與三閘極先進場效電晶體上的影響與討論。

在同時考慮線邊緣粗糙度和功函數變異程度以及基於相同的元件寬度和鰭寬度(10nm and 7nm)的比較基準下，三閘極場效電晶體的次臨界斜率(Subthreshold Slope)、臨界電壓(VT)和靜態隨機存取記憶體穩定度較不受元件變異的影響。但在隨機電報雜訊(RTN)方面，三閘極場效電晶體因為電流分布較集中於通道底部，當電荷陷阱放置在底部時會造成較大的電流變異。因此，當我們同時考慮鰭線邊緣粗糙度和功函數變異程度的情況下，三閘極場效電晶體表現出更廣的分布、更強電荷陷阱的位置依賴性以及在元件電流、臨界電壓和互導參數(gm)受到更大的影響。 我們也研究隨機電報雜訊在靜態隨機存取記憶體穩定度、維德拉電流源、邏輯電路(Inverter、NAND和Multiplexer)的漏電流和延遲的影響。我們發現隨著操作電壓的下降，隨機電報雜訊的影響隨之增加；和鰭狀場效電晶體相比，三閘極元件為基礎的電路特性將會受到較為嚴重的影響。

In this thesis, we present a comprehensive comparative analysis of FinFET and Trigate in terms of device characteristics, stability of 6T SRAM cell, logic circuits and Widlar current source. The critical intrinsic random variations, including fin Line Edge Roughness (fin LER), Work Function Variation (WFV) and single-trap-induced Random Telegraph Noise (RTN) on FinFET and Trigate devices are investigated and compared using 3D TCAD atomistic simulations.

The results indicate that Trigate device shows slightly better variability immunity in Subthreshold Slope (S.S.), threshold voltage (VT), 6T SRAM cell stability with identical electrical width and fin width (10nm and 7nm) considering fin LER and WFV simultaneously. While considering the impact of RTN, Trigate device, with larger fraction of electron current near the bottom region of the silicon fin channel, suffers larger RTN degradation for the trap located at the bottom region, whereas less impact is observed with single charged trap at the top region. As such, Trigate device exhibits broader dispersion and stronger dependence on the trap location. In the presence of fin LER and WFV, larger impact is found in RTN amplitude (ΔID/ID), nominal Δgm/gm, σ(Δgm/gm) and ΔVT with a trap placed at the worst position of Trigate MOSFET. Furthermore, the influence of RTN on 6T SRAM cell stability, Widlar current source, the leakage-delay of inverter, Two-Way NAND and 2-To-1 Multiplexer (MUX) are examined. It is observed that with degreasing supply voltage, the importance of RTN degradation increases, and that Trigate-based circuits are found to be inferior to the FinFET counterparts.

Abstract (Chinese) I
Abstract (English) II
Acknowledgement III
Contents IV
Figure Captions VI
Table Captions X

Chapter 1 Introduction 1
1.1 Background 1
1.2 Literature Review and Motivation 2
1.3 Organization 3

Chapter 2 Line Edge Roughness and Work Function Variation in FinFET and Trigate 4
2.1 Introduction 4
2.2 Line Edge Roughness (LER) 5
2.2.1 Introduction 5
2.2.2 Methodologies 6
2.2.2.1 Concept 6
2.2.2.2 Simulation Approach 6
2.2.3 Results and Discussions 8
2.3 Work Function Variation (WFV) 8
2.3.1 Introduction 8
2.3.2 Methodologies 10
2.3.2.1 Concept 10
2.3.2.2 Simulation Approach 10
2.3.3 Results and Discussions 11
2.4 Device Variability and SRAM Stability considering Fin LER/WFV 12
2.4.1 Device Variability 12
2.4.2 SRAM Stability 12
2.5 Summary 13

Chapter 3 Impact of Random Telegraph Noise in FinFET and Trigate 26
3.1 Introduction 26
3.2 Random Telegraph Noise 27
3.2.1 Introduction 27
3.2.2 Methodologies 28
3.2.3 Results and Discussions 28
3.2.3.1 FinFET and Trigate Devices 28
3.2.3.2 6T SRAM and Logic Circuits 30
3.3 Impact of RTN in the Presence of LER and WFV 32
3.3.1 FinFET and Trigate Devices 32
3.3.2 Widlar Current Source 32
3.4 Summary 33

Chapter 4 Conclusions 51

References 53
Resume 60

[1] E. Karl, W. Yih, N. Yong-Gee, G. Zheng, F. Hamzaoglu, U. Bhattacharya, K. Zhang, K. Mistry, and M. Bohr, "A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, 2012, pp. 230-232.
[2] E. Baravelli, M. Jurczak, N. Speciale, K. De Meyer, and A. Dixit, "Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance," Nanotechnology, IEEE Transactions on, vol. 7, pp. 291-298, 2008.
[3] E. Baravelli, A. Dixit, R. Rooyackers, M. Jurczak, N. Speciale, and K. De Meyer, "Impact of Line-Edge Roughness on FinFET Matching Performance," Electron Devices, IEEE Transactions on, vol. 54, pp. 2466-2474, 2007.
[4] K. Ohmori, T. Matsuki, D. Ishikawa, T. Morooka, T. Aminaka, Y. Sugita, T. Chikyow, K. Shiraishi, Y. Nara, and K. Yamada, "Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008, pp. 1-4.
[5] H. F. Dadgour, K. Endo, V. K. De, and K. Banerjee, "Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors─Part II: Implications for Process, Device, and Circuit Design," Electron Devices, IEEE Transactions on, vol. 57, pp. 2515-2525, 2010.
[6] A. R. Brown, N. M. Idris, J. R. Watling, and A. Asenov, "Impact of Metal Gate Granularity on Threshold Voltage Variability: A Full-Scale Three-Dimensional Statistical Simulation Study," Electron Device Letters, IEEE, vol. 31, pp. 1199-1201, 2010.
[7] Y. Tsukamoto, T. Seng Oon, S. Changhwan, A. Mairena, L. Tsu-Jae King, Nikolic, x, and B., "Analysis of the relationship between random telegraph signal and negative bias temperature instability," in Reliability Physics Symposium (IRPS), 2010 IEEE International, 2010, pp. 1117-1121.
[8] L. Chung-Hsun, J. Chang, M. Guillorn, A. Bryant, P. Oldiges, and W. Haensch, "Non-planar device architecture for 15nm node: FinFET or trigate?," in SOI Conference (SOI), 2010 IEEE International, 2010, pp. 1-2.
[9] S. Xin, V. Moroz, N. Damrongplasit, S. Changhwan, and L. Tsu-Jae King, "Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs," Electron Devices, IEEE Transactions on, vol. 58, pp. 3294-3299, 2011.
[10] A. V. Y. Thean, Z. H. Shi, L. Mathew, T. Stephens, H. Desjardin, C. Parker, T. White, M. Stoker, L. Prabhu, R. Garcia, B. Y. Nguyen, S. Murphy, R. Rai, J. Conner, B. E. White, and S. Venkatesan, "Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors," in Electron Devices Meeting, 2006. IEDM '06. International, 2006, pp. 1-4.
[11] H. H. Mueller and M. Schulz, "Random telegraph signal: An atomic probe of the local current in field-effect transistors," Journal of Applied Physics, vol. 83, pp. 1734-1741, 1998.
[12] Y. F. Lim, Y. Z. Xiong, N. Singh, R. Yang, Y. Jiang, D. S. H. Chan, W. Y. Loh, L. K. Bera, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, "Random Telegraph Signal Noise in Gate-All-Around Si-FinFET With Ultranarrow Body," Electron Device Letters, IEEE, vol. 27, pp. 765-768, 2006.
[13] A. Asenov, R. Balasubramaniam, A. R. Brown, and J. H. Davies, "RTS amplitudes in decananometer MOSFETs: 3-D simulation study," Electron Devices, IEEE Transactions on, vol. 50, pp. 839-845, 2003.
[14] N. Tega, H. Miki, F. Pagette, D. J. Frank, A. Ray, M. J. Rooks, W. Haensch, and K. Torii, "Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm," in VLSI Technology, 2009 Symposium on, 2009, pp. 50-51.
[15] D. Hisamoto, L. Wen-Chin, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, K. Tsu-Jae, J. Bokor, and H. Chenming, "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm," Electron Devices, IEEE Transactions on, vol. 47, pp. 2320-2325, 2000.
[16] www.intel.com.
[17] A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation study," Electron Devices, IEEE Transactions on, vol. 45, pp. 2505-2513, 1998.
[18] C. D. Young, M. O. Baykan, A. Agrawal, H. Madan, K. Akarvardar, C. Hobbs, I. Ok, W. Taylor, C. E. Smith, M. M. Hussain, T. Nishida, S. Thompson, P. Majhi, P. Kirsch, S. Datta, and R. Jammy, "Critical discussion on (100) and (110) orientation dependent transport: nMOS planar and FinFET," in VLSI Technology (VLSIT), 2011 Symposium on, 2011, pp. 18-19.
[19] Sentaurus TCAD, C2010-03 Manual, 2010, Sentaurus Device.
[20] www.itrs.net.
[21] R. Gareth, R. B. Andrew, A.-L. Fikru, R. Scott, and A. Asen, "Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs," Electron Devices, IEEE Transactions on, vol. 53, pp. 3063-3070, 2006.
[22] S. Yu, Y. Zhao, G. Du, J. Kang, R. Han, and X. Liu, "The impact of line edge roughness on the stability of a FinFET SRAM," Semiconductor Science and Technology, vol. 23, pp. 45-53, 2009.
[23] S. M. Goodnick, D. K. Ferry, C. W. Wilmsen, Z. Liliental, D. Fathy, and O. L. Krivanek, "Surface roughness at the Si(100)-SiO2 interface," Physical Review B, vol. 32, pp. 8171-8186, 1985.
[24] A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness," Electron Devices, IEEE Transactions on, vol. 50, pp. 1254-1260, 2003.
[25] P. Oldiges, L. Qimghuamg, K. Petrillo, M. Sanchez, M. Ieong, and M. Hargrove, "Modeling line edge roughness effects in sub 100 nanometer gate length devices," in Simulation of Semiconductor Processes and Devices, 2000. SISPAD 2000. 2000 International Conference on, 2000, pp. 131-134.
[26] H. Chien-Yu, F. Ming-Long, V. P. Hu, S. Pin, and C. Ching-Te, "Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 20, pp. 1201-1210, 2012.
[27] J. Hicks, D. Bergstrom, M. Hattendorf, J. Jopling, J. Maiz, S. Pae, C. Prasad, and J. Wiedemer, "45nm Transistor Reliability," Intel Technology Journal, vol. 12, pp. 131-144, 2008.
[28] H. Dadgour, K. Endo, V. De, and K. Banerjee, "Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008, pp. 1-4.
[29] Z. Xiao, L. Jing, M. Grubbs, M. Deal, B. Magyari-Kope, B. M. Clemens, and Y. Nishi, "Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4.
[30] S.-H. Chao, M.-L. Fan, and P. Su, "Investigation and Comparison of Work Function Variation for FinFET and Ultra-Thin-Body SOI Devices Using a Voronoi Approach," 2012 International Conference on. Solid State Devices and Materials (SSDM 2012).
[31] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, New York: Cambridge Univ. Press, 1998.
[32] F. J. Garcia Ruiz, A. Godoy, F. Gamiz, C. Sampedro, and L. Donetti, "A Comprehensive Study of the Corner Effects in Pi-Gate MOSFETs Including Quantum Effects," Electron Devices, IEEE Transactions on, vol. 54, pp. 3369-3377, 2007.
[33] T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hynn, Y. G. Shin, J. N. Han, I. S. Park, U. I. Chung, J. T. Moon, E. Yoon, and J. H. Lee, "Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers," in VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, 2003, pp. 135-136.
[34] K. Uchimura, T. Hayashi, T. Kimura, and A. Iwata, "Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators," Acoustics, Speech and Signal Processing, IEEE Transactions on, vol. 36, pp. 1899-1905, 1988.
[35] M. Agostinelli, J. Hicks, J. Xu, B. Woolery, K. Mistry, K. Zhang, S. Jacobs, J. Jopling, W. Yang, B. Lee, T. Raz, M. Mehalel, P. Kolar, Y. Wang, J. Sandford, D. Pivin, C. Peterson, M. DiBattista, S. Pae, M. Jones, S. Johnson, and G. Subramanian, "Erratic fluctuations of sram cache vmin at the 90nm process technology node," in Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp. 655-658.
[36] M. Bauer, R. Alexis, G. Atwood, B. Baltar, A. Fazio, K. Frary, M. Hensel, M. Ishac, J. Javanifard, M. Landgraf, D. Leak, K. Loe, D. Mills, P. Ruby, R. Rozman, S. Sweha, S. Talreja, and K. Wojciechowski, "A multilevel-cell 32 Mb flash memory," in Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International, 1995, pp. 132-133, 351.
[37] N. Tega, H. Miki, M. Yamaoka, H. Kume, M. Toshiyuki, T. Ishida, M. Yuki, R. Yamada, and T. Kazuyoshi, "Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM," in Reliability Physics Symposium, 2008. IRPS 2008. IEEE International, 2008, pp. 541-546.
[38] L. Sanghoon, C. Heung-Jae, S. Younghwan, L. Dong Seup, and S. Hyungcheol, "Characterization of oxide traps leading to RTN in high-k and metal gate MOSFETs," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4.
[39] T. Nagumo, K. Takeuchi, T. Hase, and Y. Hayashi, "Statistical characterization of trap position, energy, amplitude and time constants by RTN measurement of multiple individual traps," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 28.3.1-28.3.4.
[40] M. L. Fan, V. P. H. Hu, Y. N. Chen, P. Su, and C. T. Chuang, "Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits," Electron Devices, IEEE Transactions on, vol. PP, pp. 1-8, 2012.
[41] M.-L. Fan, V. P.-H. Hu, C. Yin-Nien, P. Su, and C.-T. Chuang, "Impacts of Random Telegraph Noise on FinFET devices, 6T SRAM cell, and logic circuits," in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. CR.1.1-CR.1.6.
[42] Y. Tsividis, Operation and modeling of the MOS transistor, London, U.K.: Oxford Univ. Press, 1999.
[43] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "Random telegraph noise of deep-submicrometer MOSFETs," Electron Device Letters, IEEE, vol. 11, pp. 90-92, 1990.
[44] F. Ming-Long, W. Yu-Sheng, H. Vita Pi-Ho, H. Chien-Yu, S. Pin, and C. Ching-Te, "Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability─A Model-Based Approach," Electron Devices, IEEE Transactions on, vol. 58, pp. 609-616, 2011.