臺灣博碩士論文加值系統

在現今的 IC 設計中，晶片的整合度與成本是相當重要的考量，因此，射頻積體電路 (radio-frequency integrated circuits, RF ICs) 也逐漸傾向於實現在 CMOS 製程中。在 CMOS 製程中，靜電放電 (electrostatic discharge, ESD) 是一項相當重要的可靠度問題，因此針對使用 CMOS 製程的射頻積體電路之靜電放電防護設計自然也是需求孔急。由於射頻積體電路對於任何額外的寄生效應都相當敏感，因此能應用在射頻積體電路之靜電放電防護設計除了要有好的靜電放電耐受度之外，還必須要能將其寄生效應的影響降至最低。
本篇論文提出了兩項可應用在射頻積體電路之靜電放電防護設計。其中之一可應用於 60 GHz 的射頻積體電路，透過適當設計的電感 (inductor) 與電容 (capacitor)，能夠在高頻下將寄生效應的影響降低，同時又能兼顧一定的靜電放電防護能力。
另外一項則為適用於射頻功率放大器 (power amplifier, PA) 之靜電放電防護設計。透過一個使用齊納二極體 (Zener diode) 來觸發的的矽控整流器 (silicon-controlled rectifier, SCR) 來做為靜電防護元件，並搭配電源端到地端間靜電放電箝制電路 (power-rail ESD clamp circuit) 來完成全晶片防護，同時搭配 2.4 GHz 之射頻功率放大器電路以作驗證。
根據量測結果，這些設計可以有效的提供射頻積體電路適當的靜電放電防護能力，同時又不會影響其正常操作。

For the consideration of high integration and low cost, radio-frequency integrated circuits (RF ICs) have been fabricated in CMOS processes. Electrostatic discharge (ESD) is one of the most serious reliability issues of CMOS processes, and it also bothers RF IC designers now. A successful RF ESD protection design needs well ESD protection ability and small parasitic effect, since RF ICs are very sensitive to any extra parasitic effect.
In this thesis, two RF ESD protection designs are proposed and verified. One is for RF circuits operating in 60 GHz. With the help of inductor and capacitor, the parasitic capacitance of ESD protection device can be effectively decreased and acceptable ESD level can be required.
The other one is for RF power amplifier (PA). A Zener-diode-triggered silicon-controlled rectifier (ZTSCR) is used as an ESD protection device. In addition, two 2.4 GHz CMOS PAs with the proposed ZTSCR and power-rail ESD clamp circuit are designed as ESD-protected PAs to verify their ESD level.
According to the experimental results, the ESD protection designs have high ESD robustness without degrading the RF performances.

Abstract (Chinese) i
Abstract (English) iii
Acknowledgment v
Contents vi
Table Captions viii
Figure Captions ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 3
Chapter 2 Basics of RF and ESD Protection 5
2.1 General Considerations of LNA Design 5
2.1.1 S-Parameters and Noise Figures 5
2.1.2 Stability 7
2.2 General Considerations of PA Design 8
2.2.1 Efficiency and Large Signal Characteristics 8
2.2.2 Load-Line Theory and Load-Pull Characterization 10
2.2.3 Classes of Conventional Linear PA 14
2.3 Conventional ESD Protection Design 15
2.3.1 Architecture of Conventional Whole-Chip ESD Protection Design 15
2.3.2 Power-Rail ESD Clamp Circuit and I/O ESD Clamp Device 16
2.4 Issues of RF ESD Protection Design 20
2.4.1 Impacts of ESD Protection Design on RF Performance 20
2.4.2 Challenges of RF ESD Protection Design 22
2.4.3 Conventional RF ESD protection designs 23
Chapter 3 ESD Protection Design for 60 GHz RF Circuits 30
3.1 Challenges of ESD Protection Design for 60 GHz RF Circuits 30
3.2 Architecture of The Proposed ESD Protection Designs 30
3.3 ESD Discharge Paths of the Proposed ESD Protection Designs 34
3.4 Simulation Results 37
3.5 Experimental Results 37
3.5.1 Test Circuits 37
3.5.2 Measured RF Performance 39
3.5.3 Measured ESD Robustness 42
3.5.4 Comparison and Discussion 43

Chapter 4 ESD Protection Design for 2.4 GHz CMOS RF PA 45
4.1 Traditional ESD Protection Design for PA 45
4.2 Proposed ESD Protection Design for PA 46
4.3 Experimental Results of ZTSCR 52
4.3.1 Test Devices 52
4.3.2 Experimental Results 53
4.4 Circuit Design of 2.4 GHz CMOS RF PA 57
4.4.1 Circuit Design 57
4.4.2 Post-Simulation Results 58
4.5 Experimental Results of 2.4 GHz CMOS PA with ZTSCR 62
4.5.1 The Layout Description of Unprotected PA and ESD-protected PA 62
4.5.2 ESD Levels Measured with HBM ESD Tester 65
4.5.3 Measured RF Performance of the Unprotected PA 68
4.5.4 Comparison of RF Performance before ESD Stress 71
4.5.5 Comparison of RF Performance after ESD Stress 74
4.6 Discussion 83
4.7 PA ESD Protection Design Consists of RF Choke Inductor and Power-Rail ESD Clamp Circuit 84
Chapter 5 Conclusions and Future Works 89
5.1 Conclusions 89
5.2 Future Works 90
Reference 91
Vita 93
Publication 94

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