臺灣博碩士論文加值系統

近幾年來，記憶體在許多電子產品中被廣泛運用，因為記憶體的高操作速度與高效能。另外，因為靜態隨機存取記憶體也比其他種類的記憶體具有更高的操作速度，所以靜態隨機存取記憶體在高性能微處理器的快取記憶體和嵌入式系統中更是被廣泛應用。過去20年間，6T 靜態隨機存取記憶體因為有較高的操作速度與較緊密的面積，因此在設計上仍然以6T靜態隨機存取記憶體為設計主流。但是隨著製程演進至深次微米等級之後，製程變異會是影響6T靜態隨機存取記憶體存活的關鍵因素。在先進製程下，這些製程變異會讓6T 靜態隨機存取記憶體的讀或寫的能力受到嚴重的退化。除了讀寫能力受到影響之外，特別是在低壓操作時，6T 靜態隨機存取記憶體幾乎是無法正常的運作。
為了設計出能在先進製程下正常運作的6T 靜態隨機存取記憶體，我們提出三步階升壓型字元線技術、適應性數據感知寫入輔助技術、位元線降壓技術以及適應性電壓偵測技術來提高讀寫能力與降低閘極氧化層被擊穿的機會。此外，為了提高操作速度我們也運用管線化技巧。在本論文中，我們將這些技術、2階級管線化技術與單電源電壓設計在一顆1.0Mb高性能6T 靜態隨機存取記憶體，並且透過下線將該晶片實現在40奈米低功耗互補金屬氧化物半導體技術上。該晶片可以工作在寬電壓範圍從 1.2V至0.7V，具有工作平率900MHz@1.1V 和 25oC。

In recent years, memories have been widely used for the most electronic products due to their high operation speed and high performance. Besides, Due to SRAMs have higher operating speed than other memory family, SRAMs have been widely used for the high-performance microprocessor cache and embedded system. During the past 20 years, standard 6T SRAM cell becomes the mainstream of SRAMs design due to its highest speed and compact area. However, with the scaling into the deep sub-micron of process, the process variation affects the subsistence of the 6T SRAM cell. In advance technology node, the read and write ability suffer a serious degradation by theses process variation. Especially, at low operation voltage, 6T SRAM cell almost couldn’t have normal operation.
In order to design the 6T SRAM that it can normal work in the advanced process, we proposed the Three Step-Up Word-Line technique, Adaptive-Data-Aware Write-Assist technique, Bit-Line Under-Drive Read-Assist technique, and Adaptive Voltage Detector technique to enhance the read/write ability and performance, and reduce the gate oxide to be punctured. Besides, in order to enhance operating speed, we also applied the pipeline technique to enhance the operating speed. In the thesis, we design a 1.0Mb high-performance 6T SRAM with these techniques with two stage pipeline technique with a single supply voltage, and implement by way of tape out in the 40nm Low- Power complementary metal-oxide semiconductor technology. The chip has wide voltage range from 1.5V to 0.6V, with operating frequency of 900MHz@1.1V and 25℃.

Content

CHAPTER 1 INTRODUCTION 1
1.1 BACKGROUND 1
1.2 MOTIVATION AND GOALS 2
1.3 THESIS ORGANIZATION 2
CHAPTER 2 OVERVIEW OF THE DESIGN OF 6T SRAM 4
2.1 MEMORY FAMILY 4
2.2 6T SRAM 5
2.2.1 Structure of 6T SRAM 5
2.2.2 Read Operation and Read Disturb of 6T SRAM 6
2.2.3 Hold Static Noise Margin and Read Static Noise Margin 8
2.2.4 Write Operation and Half-Selected Read Disturb of 6T SRAM 10
2.2.5 Write Static Noise Margin and Write Margin and AC Write Margin 12
2.2.6 The Size and Layout of 6T SRAM 14
2.3 SRAM ARRAY ARCHITECTURE 15
2.3.1 Memory Array 15
2.3.2 Differential Sensing and Large Signal Sensing Scheme 17
2.3.3 Non-Pipeline SRAM Design 21
2.3.4 Pipeline SRAM Design 22
2.4 GLOBAL VARIATION AND LOCAL VARIATION ISSUE 26
2.5 THE DESIGN METHODOLOGY OF 6T SRAM 28
2.5.1 Dual Supplies 29
2.5.2 Dynamic Bit-Line Level 31
2.5.3 Dynamic Word-Line Level 32
2.5.4 Negative Bit-Line Level 34
CHAPTER 3 DESIGN OF 1.0MB 6T PIPELINE SRAM WITH THREE STEP-UP WORD-LINE AND BIT-LINE UNDER DRIVE AND ADAPTIVE VOLTAGE DETECTOR SKILL 37
3.1 INTRODUCTION 37
3.2 PROPOSED BIT-LINE UNDER-DRIVE (BLUD) TECHNIQUE 40
3.3 PROPOSED THREE STEP-UP WORD-LINE (TSUWL) TECHNIQUE 47
3.4 PROPOSED ADAPTIVE VOLTAGE DETECTOR (AVD) TECHNIQUE 57
3.5 MACRO IMPLEMENTATION AND SIMULATION RESULT 58
3.6 TEST FLOW 69
3.7 IMPLEMENTATION AND MEASUREMENT RESULT OF TEST CHIP 70
CHAPTER 4 CONCLUSIONS 75
REFERENCE OF CHAPTER 2 76
REFERENCE OF CHAPTER 3 80

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