跳到主要內容

臺灣博碩士論文加值系統

(18.97.14.87) 您好!臺灣時間:2025/01/17 18:56
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:倪嘉隆
研究生(外文):Ni, Chia-Lung
論文名稱:具有線電壓重建及總諧波失真最佳化以達到0.99功率因數及1.7%總諧波失真之功率因數校正控制器
論文名稱(外文):0.99 PF and 1.7% THD by Line Voltage Recovery and Total Harmonic Distortion Optimizer in Power Factor Correction Controller
指導教授:陳科宏陳科宏引用關係
指導教授(外文):Chen, Ke-Horng
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電控工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:101
語文別:英文
論文頁數:50
中文關鍵詞:功率因數總諧波失真線電壓重建
外文關鍵詞:power factortotal harmonic distortionline voltage recovery
相關次數:
  • 被引用被引用:0
  • 點閱點閱:568
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
隨著人口的增加以及各國的工業化,世界對於能源的需求也逐漸增加,近幾年來,能源短缺的問題變得越來越嚴重,因此,綠能的議題漸漸地被受到重視。功率因數校正可以調整隔離式電源供應器產生的電流與輸入交流電壓形成同相位,使得可利用的實功最大化,達到高功率因數的效果。輸入電流的總諧波失真是一個影響功率因數的重要因子。對於類似像變壓器及照明設備這些低瓦數的應用,考量到為了維持高功率因數和高效率,臨界導通模式是一個較適合的控制方式。然而,傳統的臨界導通模式之功率因數升壓轉換器有著兩個主要的失真問題,一種是因為橋式整流器的導通電壓以及寄生電容而造成的交越失真,另一種是線電壓頻率反射失真。由於失真造成的諧波電流會對其它電子設備產生嚴重的影響,因此在國際上有許多限制諧波電流的規範,為了符合日趨嚴格的諧波規範,在本篇論文中,提出了一個有效改善總諧波失真的技術。
在一個寬範圍的輸入線電壓中,本論文所提出的線電壓重建技術與總諧波失真最佳化技術可以有效地增進功率因數與改善總諧波失真。線電壓重建技術可偵測輸入線電壓的方均根值並且產生等效的數位碼給總諧波失真最佳化技術利用,總諧波失真最佳化技術依據收到的數位碼合適地去調整導通時間,即使對於不同的線電壓輸入,都可達到總諧波失真最佳化的效果。另外藉著線電壓重建技術與總諧波失真最佳化技術提供了一條前饋路徑使得回受電壓漣波減小,更進一步地去改善總諧波失真。因此,本論文所提出的功率因數校正控制器,即使在一個寬範圍的輸入線電壓中,仍然可以維持高功率因數及低總諧波失真的表現。實驗結果顯示,藉由本論文提出的技術,功率因數可高於0.99,並且在輸入交流電壓為90伏特及110伏特時,總諧波失真為1.7%,其測試電路利用台灣積體電路公司八百伏特超高壓製程實現。

As populations increase and countries industrialize, the world’s demand for energy increases. In recent years, the energy-shortage problem becomes more serious. Therefore, the issue of green power is respected gradually. Power factor correction (PFC) can shape the input current of off-line power supplies to be in-phase with the input AC voltage in order to maximize the available real power from the AC source to achieve high power factor (PF). The total harmonic distortion (THD) of input current is an important factor for PF. Considering high power factor (PF) and efficiency, the boundary conduction mode (BCM) control is more suitable for low-power applications such as the adapter and lighting. However, there are two major THD-deteriorated contributors in a conventional PFC boost converter with BCM control. One is the crossover distortion caused by the diode’s forward voltage in the bridge and parasitic capacitances. The other is the line frequency reflected distortion. Because the harmonic current can interfere with other electronic equipment seriously, there are many international standards to limit harmocin current. In order to conform the harmonic-current standards stricter and stricter, an improving THD technique is proposed in this thesis.
The proposed line voltage recovery (LVR) and the total harmonic distortion optimizer (THDO) improve PF and THD over a wide line voltage range. The LVR detects the input line root-mean-square (rms) voltage to generate the digital equivalent code to the THDO for optimizing the THD by tuning the on-time value at different line voltages. Besides, the LVR and the THDO provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC controller can keep high PF and low THD over a wide line voltage. Experimental results demonstrate the PF is higher than 0.99 and the THD is 1.7% at VAC of 90 - 110V by the test circuit fabricated in TSMC 800V UHV process.

Chapter 1 1
Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Thesis Organization 5
Chapter 2 6
Fundamentals of PFC 6
2.1 The Relationship between PF and THD 6
2.2 Classification of PFC 8
2.3 Control Modes of PFC Boost Converter 10
2.4 Principle of PFC Boost Converter with BCM 12
Chapter 3 15
Proposed Line Voltage Recovery and Total Harmonic Distortion Optimizer in Power Factor Correction Controller 15
3.1 Line Reflected Frequency Distortion 15
3.2 Crossover Distortion 17
3.3 Proposed Architecture 22
Chapter 4 24
Circuit Implementation 24
4.1 Proposed Line Voltage Recovery (LVR) 24
4.2 Proposed Total Harmonic Distortion Optimizer (THDO) 27
4.3 Zero Current Detector (ZCD) 33
4.4 Output Driver 35
Chapter 5 36
Experimental Results 36
5.1 Chip Micrograph and Design Specifications 36
5.2 LVR Function 37
5.3 The Clamped Function of ZCD 38
5.4 THDO 39
5.5 Measured Output Voltage and Input Line Current 42
5.6 Measured THD and PF 44
5.7 Comparison with Prior Arts 46
Chapter 6 47
Conclusions and Future Work 47
6.1 Conclusions 47
6.2 Future Work 47
Reference 48
[1] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed., Norwell, MA: Kluwer Academic Publishers, 2001.
[2] A. Fernandez, J. Sebastian, M. M. Hernando, P. Villegas, and J. Garcia, “Helpful Hints to Select a Power-Factor-Correction Solution for Low-and Medium-Power Single-Phase Power Supply,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 46-55, Feb. 2005.
[3] O.Gracia, J. A. Cobos, R. Prieto, and J. Uceda, “Single-Phase Power Factor Correction: a Survey,” IEEE Trans. Power Electron., vol. 18, no.3, pp. 749-755, May 2003.
[4] J. Sebastian, M. Jaureguizar, and J. Uceda, “An Overview of Power Factor Correction in Single-Phase Off-Line Power Supply Systems,” in Proc. IEEE IECON’94, vol. 3, pp. 1688-1693, Sep. 1994.
[5] J. Sun, W. C. Wu, and R. M. Bass, “Large-Signal Characterization of Single-Phase PFC Circuits with Different Types of Current Control,” in Proc. IEEE Applied Power Electronics Conf., pp. 655-661, Feb. 1998.
[6] S. F. Lim and A. M. Khambadkone, “A simple digital DCM control scheme for boost PFC operating in both CCM and DCM,” IEEE Trans. Industry Applications, vol.47, no. 4, pp.1802-1812, July-Aug. 2011.
[7] F. Z. Chen and D. Maksimovic, “Digital control for improved efficiency and reduced harmonic distortion over wide load range in boost PFC rectifiers,” IEEE Trans. Power Electron., vol. 25, no. 10, pp. 2683-2692, Oct. 2010.
[8] H. S. Athab and P. K. Shadhu Khan, “A cost effective method of reducing total harmonic distortion (THD) in single-phase boost rectifier,” in Proc. IEEE Power Electron. Drive Syst. Conf., pp. 669-674, Nov. 2007.
[9] J. W. Kim, S. M. Choi, and K. T. Kim, “Variable on-time control of the critical conduction mode boost power factor correction converter to improve zero-crossing distortion,” in Proc. IEEE Power Electron. Drive Syst. Conf., pp. 1542-1546, Nov. 2005.
[10] S. H. Tang, D. Chen, C. S. Huang, C. Y. Liu, and H. Liu, “A new on-time adjustment scheme for the reduction of input current distortion of critical-mode power factor correction boost converters,” in Proc. IEEE Int. Power Electron. Conf., 2010, pp. 1717-1724.
[11] J. Sun, “On the zero-crossing distortion in single-phase PFC converters,” IEEE Trans. Power Electron., vol.19, no.3, pp. 685-692, May 2004.
[12] J. C. P. Liu, C. K. Tse, and N. K. Poon, “A PFC voltage regulator with low input current distortion derived from a rectifierless topology,” IEEE Trans. Power Electron., vol.21, no.4, pp. 906-911, July 2006.
[13] STMicroelectronics, "L6562 datasheet: transition-mode PFC controller," Rev. 8, Nov. 2005.
[14] J. S. Lai and D. Chen, “Design consideration for power factor correction boost converter operating at the boundary of continuous and discontinuous conduction mode,” in Proc. IEEE Applied Power Electronics Conf., pp. 267-273, Mar. 1993.
[15] J. Sebastian, J. A. Cobos, J. M. Lopera, and J. Uceda, “The determination of the boundaries between continuous and discontinuous modes in PWM dc-to-dc converters used as power factor preregulator,” IEEE Trans. Power Electron., vol. 10, no. 5, pp. 574-582, Sep. 1995.
[16] K. Yao, X. Ruan, X. Mao and Z. Ye, “Variable-duty-cycle control to achieve high input power factor for DCM boost PFC converter,” IEEE Trans. Ind. Electron., vol.58, no.5, pp. 1856-1865, May 2011.
[17] H. S. Athab, “Single-phase single-switch boost PFC reglator with low total harmonic dustortion and feedforward input voltage,” in Proc. IEEE Int. Power and Energy Conf., pp. 1118-1123, Dec. 2008.
[18] J. C. Tsai, C. L. Chen, Y. T. Chen, C. L. Ni, C. Y. Chen, K. H. Chen, C. J. Chen and H. L. Pan, “Perturbation on-time (POT) control and inhibit time control (ITC) in suppression of THD of power factor correction (PFC) Design” in Proc. CICC, pp. 1-4, Sep. 2011.
[19] Koen De Gusseme, D. M. Van de Sype, A. P. M. Van Den Bossche, and J. A. Melkebeek, “Input-current distortion of CCM boost PFC converters operated in DCM,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 858-865, Apr. 2007.
[20] C. Y. Bernd and R. Liang, “Power Factor Correction with Reduced Total Harmonic Distortion,” United States Patent 6,128,205, Oct 3, 2000.
[21] Fairchild Semiconductor, "SG6901A datasheet: CCM PFC/flyback PWM combination controller," Rev. 1.0.2, Feb. 2009.
[22] Y. H. Lee, S. J. Wang, and K. H. Chen, “Quadratic differential and integration technique in V2 control buck converter with small ESR capacitor,” IEEE Trans. Power Electron., vol. 25, no. 4, pp. 829-838, Apr. 2010.
[23] Y. Y. Mai and P. K. T. Mok, “A constant frequency output-ripple-voltage-based buck converter without using large ESR capacitor,” IEEE Trans. Circuit Syst. II, Exp. Brief, vol. 55, no. 8, pp. 748-752, Aug. 2008.
[24] C. K. Chava and J. Silva-Martinez, “A frequency compensation scheme for LDO voltage regulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 6, pp. 1041-1050, Jun. 2004.

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊