臺灣博碩士論文加值系統

本論文提出兩組適合氮化鎵電晶體的上橋電路和一組下橋電路。不同於一般加強型驅動電路，此架構是針對空乏型電晶體設計，可提供穩定的負閘－源極電壓，控制功率電晶體的開關。
而針對上橋驅動電路，分別設計了1.自舉式電容電路、2.不需高崩潰電壓元件電路，兩組上橋驅動電路。自舉式電容電路提供功率元件穩定的閘－源極電壓；再利用位準調節電路將邏輯訊號轉換成適當的控制訊號。為了提升此電路的效能，本研究設計一個閂鎖電路，並與位準調節電路結合，減少其開啟的時間，以降低功率損耗，由於空乏型元件的Normally-on特性提出一個簡單的啟動電路，使自舉式電容有足夠的時間可以充電。不需高崩潰電壓電路設計的特點在於採用電容來承受高電壓差，因此相關的電晶體、二極體皆不需承受高電壓差，可由一般IC製程來製作，藉此降低驅動電路的製作成本。
此兩電路皆經HSPICE模擬驗證，不需高崩潰電壓元件電路在操作條件24V/1kHz下可正常操作，而自舉式電容驅動在48V/100kHz下可正常操作，也利用離散元件實際完成，並驗證可正常驅動氮化鎵功率電晶體。最後也完成電路布局設計，並且申請CIC的D35製程下線。

This thesis proposed a proper and complete high/low side gate drive circuit for GaN transistors. Unlike the conventional enhancement mode driver, this circuit designed for the depletion mode transistors, providing a negative gate-source voltage to turn off the power transistors.
In the high side drive circuit, we design: 1. bootstrap high side circuit. 2. Needless high breakdown voltage element two kind of configuration to drive GaN/AlGaN transistors. The first method, we used a bootstrap circuit to provide a stable gate-source voltage for the power devices, and then transferred the logic signals into the appropriate control signals by the level shifter. In order to maintain high efficiency and reduce the power consumption of this circuit, the study designed a latch circuit, which combined with the level shifter to decrease the operating time. For the bootstrap capacitor charging problem, which was due to the “normally-on” property of the depletion mode transistor, the study also designed a start-up circuit to control the timing of the initial activation of the devices. Therefore, the bootstrap capacitor would have enough lead time to charge. The second method, we used two of capacitors to endure the high voltage from others elements. Therefore, the relative transistors in this circuit would not sustain high voltage. In general, high breakdown voltage elements need a special process. The special process is necessary in this configuration, so we can reduce the cost IC produce.
Both gate driver circuits are designed and simulated using HSPICE, and then verified by experimental results. In the first gate driver design, the experimental results show that it can work at 48V/100kHz.. In the second gate driver design, the GaN transistors can work at condition 24V/1kHz. Finally, we complete the circuit layout and apply for D35 process from CIC.

中文摘要………………………………………………………I
英文摘要……………………………………………………II
誌謝………………………………………………………IV
目錄……………………………………………………………V
圖目錄………………………………………………………IX
第一章 緒論 ......................................1
1.1 氮化鎵電晶體發展背景與簡介……………………………1
(a)高操作溫度及高崩潰電壓…………………………………2
(b)高切換頻率………………………………………………3
(c)低導通電阻及高操作電流…………………………………3
(d)導通電阻的正溫度係數……………………………………4
1.2 閘極驅動電路運用…………………………………………6
(a)直流轉換器………………………………………………6
(b)變頻器……………………………………………………8
1.3 研究動機與目的…………………………………………9
1.4 論文章節組織與安排……………………………………10
第二章 閘極驅動電路介紹…………………………………11
2.1簡介………………………………………………………11
2.2下橋閘極驅動電路介紹…………………………………12
2.3 上橋閘極驅動電路介紹…………………………………13
2.3.1自舉式電路與電位位準轉換電路………………………14
2.3.2光耦合器………………………………………………18
2.4 空乏型閘極驅動電路介紹………………………………19
(a)下橋空乏型驅動電路……………………………………20
(b)上橋空乏型驅動電路……………………………………21
第三章 氮化鎵電晶體閘極驅動電路設計…………………23
3.1下橋閘極驅動電路………………………………………23
3.1.1 電路運作方式………………………………………23
3.1.2 下橋驅動電路模擬結果 ……………………………26
3.1.3 下橋驅動電路實驗結果 ……………………………27
3.2 氮化鎵上橋閘極驅動電路 ……………………………28
3.2.1 閂鎖電路…………………………………………29
3.2.2 高壓位準調節電路 …………………………………30
3.2.3 啟動電路…………………………………………32
3.3 自舉式上橋驅動電路HSPICE模擬結果………………34
3.4 自舉式上橋驅動電路實驗結果…………………………38
3.5 自舉式上橋驅動電路IC佈局圖…………………………41
第四章 不需高崩潰電壓元件之氮化鎵上橋驅動電路……42
4.1 不需高崩潰電壓元件驅動電路介紹……………………42
4.2 不需高崩潰電壓元件上橋驅動電路設計………………48
4.3 不需高崩潰電壓元件上橋驅動電路HSPICE模擬結…51
4.4 不需高崩潰電壓元件上橋驅動電路實驗結果…………53
4.5 不需高崩潰電壓元件上橋驅動電路IC佈局圖………55
4.6 不需高崩潰電壓元件上橋驅動電路改善………………56
4.7 不需高崩潰電壓元件上橋驅動電路改善模擬…………57
4.8 不需高崩潰電壓元件上橋驅動電路改善實驗…………58
第五章 結論與未來計畫……………………………………59
5.1 結論………………………………………………………59
5.2 未來計畫…………………………………………………60
參考文獻……………………………………………………61

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